[llvm-branch-commits] [llvm] [GlobalISel] Add computeNumSignBits for G_BUILD_VECTOR. (PR #139506)
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Sun May 11 23:55:30 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: David Green (davemgreen)
<details>
<summary>Changes</summary>
The code is similar to SelectionDAG::ComputeNumSignBits, but does not deal with truncating buildvectors.
---
Full diff: https://github.com/llvm/llvm-project/pull/139506.diff
3 Files Affected:
- (modified) llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp (+17)
- (modified) llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll (+10-18)
- (modified) llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll (+22-24)
``````````diff
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index fb483ed962270..999bae6ccf42c 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -874,6 +874,23 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
SrcTy.getScalarSizeInBits());
break;
}
+ case TargetOpcode::G_BUILD_VECTOR: {
+ // Collect the known bits that are shared by every demanded vector element.
+ FirstAnswer = TyBits;
+ for (unsigned i = 0, e = MI.getNumOperands() - 1; i < e; ++i) {
+ if (!DemandedElts[i])
+ continue;
+
+ unsigned Tmp2 = computeNumSignBits(MI.getOperand(i + 1).getReg(),
+ APInt(1, 1), Depth + 1);
+ FirstAnswer = std::min(FirstAnswer, Tmp2);
+
+ // If we don't know any bits, early out.
+ if (FirstAnswer == 1)
+ break;
+ }
+ break;
+ }
case TargetOpcode::G_SHUFFLE_VECTOR: {
// Collect the minimum number of sign bits that are shared by every vector
// element referenced by the shuffle.
diff --git a/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll b/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
index d86cbf57a65f3..295863f18fd41 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
@@ -61,9 +61,9 @@ define <4 x i32> @dupsext_v4i16_v4i32(i16 %src, <4 x i16> %b) {
; CHECK-GI-LABEL: dupsext_v4i16_v4i32:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: sxth w8, w0
-; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #0
; CHECK-GI-NEXT: dup v1.4s, w8
-; CHECK-GI-NEXT: mul v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: xtn v1.4h, v1.4s
+; CHECK-GI-NEXT: smull v0.4s, v1.4h, v0.4h
; CHECK-GI-NEXT: ret
entry:
%in = sext i16 %src to i32
@@ -108,16 +108,9 @@ define <2 x i64> @dupsext_v2i32_v2i64(i32 %src, <2 x i32> %b) {
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-GI-NEXT: sxtw x8, w0
-; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #0
; CHECK-GI-NEXT: dup v1.2d, x8
-; CHECK-GI-NEXT: fmov x9, d0
-; CHECK-GI-NEXT: mov x11, v0.d[1]
-; CHECK-GI-NEXT: fmov x8, d1
-; CHECK-GI-NEXT: mov x10, v1.d[1]
-; CHECK-GI-NEXT: mul x8, x8, x9
-; CHECK-GI-NEXT: mul x9, x10, x11
-; CHECK-GI-NEXT: mov v0.d[0], x8
-; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: xtn v1.2s, v1.2d
+; CHECK-GI-NEXT: smull v0.2d, v1.2s, v0.2s
; CHECK-GI-NEXT: ret
entry:
%in = sext i32 %src to i64
@@ -293,15 +286,14 @@ define <4 x i32> @nonsplat_shuffleinsert2(<4 x i16> %b, i16 %b0, i16 %b1, i16 %b
; CHECK-GI-LABEL: nonsplat_shuffleinsert2:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: sxth w8, w0
-; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #0
-; CHECK-GI-NEXT: mov v1.s[0], w8
-; CHECK-GI-NEXT: sxth w8, w1
-; CHECK-GI-NEXT: mov v1.s[1], w8
+; CHECK-GI-NEXT: sxth w9, w1
+; CHECK-GI-NEXT: fmov s1, w8
; CHECK-GI-NEXT: sxth w8, w2
-; CHECK-GI-NEXT: mov v1.s[2], w8
+; CHECK-GI-NEXT: mov v1.h[1], w9
+; CHECK-GI-NEXT: mov v1.h[2], w8
; CHECK-GI-NEXT: sxth w8, w3
-; CHECK-GI-NEXT: mov v1.s[3], w8
-; CHECK-GI-NEXT: mul v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: mov v1.h[3], w8
+; CHECK-GI-NEXT: smull v0.4s, v1.4h, v0.4h
; CHECK-GI-NEXT: ret
entry:
%s0 = sext i16 %b0 to i32
diff --git a/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll b/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
index b89b422c8c5ad..418113a4e4e09 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
@@ -108,11 +108,12 @@ define void @matrix_mul_signed(i32 %N, ptr nocapture %C, ptr nocapture readonly
;
; CHECK-GI-LABEL: matrix_mul_signed:
; CHECK-GI: // %bb.0: // %vector.header
-; CHECK-GI-NEXT: sxth w9, w3
+; CHECK-GI-NEXT: sxth w8, w3
; CHECK-GI-NEXT: // kill: def $w0 killed $w0 def $x0
+; CHECK-GI-NEXT: dup v0.4s, w8
; CHECK-GI-NEXT: sxtw x8, w0
-; CHECK-GI-NEXT: dup v0.4s, w9
; CHECK-GI-NEXT: and x8, x8, #0xfffffff8
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
; CHECK-GI-NEXT: .LBB1_1: // %vector.body
; CHECK-GI-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-GI-NEXT: add x9, x2, w0, sxtw #1
@@ -120,10 +121,8 @@ define void @matrix_mul_signed(i32 %N, ptr nocapture %C, ptr nocapture readonly
; CHECK-GI-NEXT: ldp d1, d2, [x9]
; CHECK-GI-NEXT: add x9, x1, w0, sxtw #2
; CHECK-GI-NEXT: add w0, w0, #8
-; CHECK-GI-NEXT: sshll v1.4s, v1.4h, #0
-; CHECK-GI-NEXT: sshll v2.4s, v2.4h, #0
-; CHECK-GI-NEXT: mul v1.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: mul v2.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: smull v1.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT: smull v2.4s, v0.4h, v2.4h
; CHECK-GI-NEXT: stp q1, q2, [x9]
; CHECK-GI-NEXT: b.ne .LBB1_1
; CHECK-GI-NEXT: // %bb.2: // %for.end12
@@ -305,40 +304,39 @@ define void @larger_smull(ptr nocapture noundef readonly %x, i16 noundef %y, ptr
; CHECK-GI-NEXT: b.le .LBB3_7
; CHECK-GI-NEXT: // %bb.1: // %for.body.preheader
; CHECK-GI-NEXT: sxth w8, w1
-; CHECK-GI-NEXT: mov x9, xzr
+; CHECK-GI-NEXT: mov x10, xzr
; CHECK-GI-NEXT: cmp w3, #16
-; CHECK-GI-NEXT: mov w10, w3
+; CHECK-GI-NEXT: mov w9, w3
; CHECK-GI-NEXT: b.lo .LBB3_5
; CHECK-GI-NEXT: // %bb.2: // %vector.ph
; CHECK-GI-NEXT: dup v0.4s, w8
-; CHECK-GI-NEXT: and x9, x10, #0xfffffff0
+; CHECK-GI-NEXT: and x10, x9, #0xfffffff0
; CHECK-GI-NEXT: add x11, x2, #32
; CHECK-GI-NEXT: add x12, x0, #16
-; CHECK-GI-NEXT: mov x13, x9
+; CHECK-GI-NEXT: mov x13, x10
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
; CHECK-GI-NEXT: .LBB3_3: // %vector.body
; CHECK-GI-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-GI-NEXT: ldp q1, q2, [x12, #-16]
; CHECK-GI-NEXT: mov x14, x11
; CHECK-GI-NEXT: subs x13, x13, #16
; CHECK-GI-NEXT: add x12, x12, #32
-; CHECK-GI-NEXT: sshll v3.4s, v1.4h, #0
-; CHECK-GI-NEXT: sshll2 v1.4s, v1.8h, #0
-; CHECK-GI-NEXT: sshll v4.4s, v2.4h, #0
-; CHECK-GI-NEXT: sshll2 v2.4s, v2.8h, #0
-; CHECK-GI-NEXT: mul v3.4s, v0.4s, v3.4s
-; CHECK-GI-NEXT: mul v1.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: mul v4.4s, v0.4s, v4.4s
-; CHECK-GI-NEXT: mul v2.4s, v0.4s, v2.4s
-; CHECK-GI-NEXT: stp q3, q1, [x14, #-32]!
-; CHECK-GI-NEXT: stp q4, q2, [x11], #64
+; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: mov d4, v2.d[1]
+; CHECK-GI-NEXT: smull v1.4s, v0.4h, v1.4h
+; CHECK-GI-NEXT: smull v2.4s, v0.4h, v2.4h
+; CHECK-GI-NEXT: smull v3.4s, v0.4h, v3.4h
+; CHECK-GI-NEXT: smull v4.4s, v0.4h, v4.4h
+; CHECK-GI-NEXT: stp q1, q3, [x14, #-32]!
+; CHECK-GI-NEXT: stp q2, q4, [x11], #64
; CHECK-GI-NEXT: b.ne .LBB3_3
; CHECK-GI-NEXT: // %bb.4: // %middle.block
-; CHECK-GI-NEXT: cmp x9, x10
+; CHECK-GI-NEXT: cmp x10, x9
; CHECK-GI-NEXT: b.eq .LBB3_7
; CHECK-GI-NEXT: .LBB3_5: // %for.body.preheader1
-; CHECK-GI-NEXT: add x11, x2, x9, lsl #2
-; CHECK-GI-NEXT: add x12, x0, x9, lsl #1
-; CHECK-GI-NEXT: sub x9, x10, x9
+; CHECK-GI-NEXT: add x11, x2, x10, lsl #2
+; CHECK-GI-NEXT: add x12, x0, x10, lsl #1
+; CHECK-GI-NEXT: sub x9, x9, x10
; CHECK-GI-NEXT: .LBB3_6: // %for.body
; CHECK-GI-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-GI-NEXT: ldrsh w10, [x12], #2
``````````
</details>
https://github.com/llvm/llvm-project/pull/139506
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