[llvm-branch-commits] [llvm] [SPARC][IAS] Add definitions for UA 2005 instructions (PR #138400)

[via llvm-branch-commits]

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@@ -152,13 +155,15 @@ def : Proc<"ultrasparc3",     [FeatureV9, FeatureV8Deprecated, FeatureVIS,
                                FeatureVIS2],
                               [TuneSlowRDPC]>;
 def : Proc<"niagara",         [FeatureV9, FeatureV8Deprecated, FeatureVIS,
-                               FeatureVIS2]>;
+                               FeatureVIS2, FeatureUA2005]>;
 def : Proc<"niagara2",        [FeatureV9, FeatureV8Deprecated, UsePopc,
-                               FeatureVIS, FeatureVIS2]>;
+                               FeatureVIS, FeatureVIS2, FeatureUA2005]>;
 def : Proc<"niagara3",        [FeatureV9, FeatureV8Deprecated, UsePopc,
-                               FeatureVIS, FeatureVIS2, FeatureVIS3]>;
+                               FeatureVIS, FeatureVIS2, FeatureVIS3,
+                               FeatureUA2005]>;
 def : Proc<"niagara4",        [FeatureV9, FeatureV8Deprecated, UsePopc,
-                               FeatureVIS, FeatureVIS2, FeatureVIS3]>;
+                               FeatureVIS, FeatureVIS2, FeatureVIS3,
+                               FeatureUA2005]>;
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koachan wrote:

I usually refer to the supplement documents ([T1](https://www.oracle.com/docs/tech/systems/t1-09-ust1-uasuppl-draft-hp-ext.pdf) [T2](https://www.oracle.com/docs/tech/systems/t2-14-ust2-uasuppl-draft-hp-ext.pdf) [T3](https://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparct3-implem-supp-2516665.pdf) [T4](https://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/120214-t4-d04-p-ext-2305974.pdf) are the most relevant, there also exist [M5](https://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/140529-m5-d07-p-ext-2306120.pdf) and [M7](https://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-architecture-supplement-3093429.pdf) ones if we do get around to implement optimization/ISA extension support for those processors).

https://github.com/llvm/llvm-project/pull/138400