[llvm-branch-commits] [llvm] [SPARC][MC] Add tests for VIS family instructions (PR #130967)
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Tue Mar 25 08:08:28 PDT 2025
https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/130967
>From e2e0d44800b65a8fbddd6234c2ee9f83af92d7da Mon Sep 17 00:00:00 2001
From: Koakuma <koachan at protonmail.com>
Date: Wed, 12 Mar 2025 21:14:42 +0700
Subject: [PATCH 1/3] Add missing NO-VIS lines
Created using spr 1.3.5
---
llvm/test/MC/Sparc/sparc-vis.s | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/llvm/test/MC/Sparc/sparc-vis.s b/llvm/test/MC/Sparc/sparc-vis.s
index bf01da19293d0..bed901b6a7272 100644
--- a/llvm/test/MC/Sparc/sparc-vis.s
+++ b/llvm/test/MC/Sparc/sparc-vis.s
@@ -199,28 +199,39 @@ fcmpeq16 %f0, %f2, %o0
! VIS: fcmpeq32 %f0, %f2, %o0 ! encoding: [0x91,0xb0,0x05,0xc2]
fcmpeq32 %f0, %f2, %o0
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: edge8 %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x00,0x09]
edge8 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: edge8l %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x00,0x49]
edge8l %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: edge16 %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x00,0x89]
edge16 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: edge16l %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x00,0xc9]
edge16l %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: edge32 %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x01,0x09]
edge32 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: edge32l %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x01,0x49]
edge32l %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: pdist %f0, %f2, %f4 ! encoding: [0x89,0xb0,0x07,0xc2]
pdist %f0, %f2, %f4
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: array8 %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x02,0x09]
array8 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: array16 %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x02,0x49]
array16 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: array32 %o0, %o1, %o2 ! encoding: [0x95,0xb2,0x02,0x89]
array32 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
! VIS: shutdown ! encoding: [0x81,0xb0,0x10,0x00]
shutdown
>From b98295fcdaa9fc1d6a839956c304dd5a7d31cc24 Mon Sep 17 00:00:00 2001
From: Koakuma <koachan at protonmail.com>
Date: Wed, 12 Mar 2025 22:27:36 +0700
Subject: [PATCH 2/3] Fix typo in comment
Created using spr 1.3.5
---
llvm/lib/Target/Sparc/SparcInstrVIS.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/Sparc/SparcInstrVIS.td b/llvm/lib/Target/Sparc/SparcInstrVIS.td
index 6d0f12da3afcf..fbf56ae22cd30 100644
--- a/llvm/lib/Target/Sparc/SparcInstrVIS.td
+++ b/llvm/lib/Target/Sparc/SparcInstrVIS.td
@@ -7,7 +7,7 @@
//===----------------------------------------------------------------------===//
//
// This file contains instruction formats, definitions and patterns needed for
-// VIS, VIS II, VIS II instructions on SPARC.
+// VIS, VIS II, VIS III instructions on SPARC.
//===----------------------------------------------------------------------===//
// VIS Instruction Format.
>From 618c4853f63fa60bd6d6d0e9ec69d6149e2b2137 Mon Sep 17 00:00:00 2001
From: Koakuma <koachan at protonmail.com>
Date: Sun, 23 Mar 2025 20:51:40 +0700
Subject: [PATCH 3/3] Apply suggestions
Created using spr 1.3.5
---
llvm/lib/Target/Sparc/SparcInstrFormats.td | 4 ++--
llvm/lib/Target/Sparc/SparcInstrInfo.td | 3 ++-
llvm/lib/Target/Sparc/SparcInstrVIS.td | 2 +-
llvm/test/MC/Sparc/sparc-vis.s | 2 +-
llvm/test/MC/Sparc/sparc-vis2.s | 2 +-
llvm/test/MC/Sparc/sparc-vis3.s | 2 +-
6 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/Sparc/SparcInstrFormats.td b/llvm/lib/Target/Sparc/SparcInstrFormats.td
index 7d32cd8e5671b..3ddb485923fcc 100644
--- a/llvm/lib/Target/Sparc/SparcInstrFormats.td
+++ b/llvm/lib/Target/Sparc/SparcInstrFormats.td
@@ -205,7 +205,7 @@ class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
class F3_3_siam<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
: F3<outs, ins, asmstr, pattern, itin> {
- bits<3> siam_mode;
+ bits<3> uimm3;
let op = opVal;
let op3 = op3val;
@@ -213,7 +213,7 @@ class F3_3_siam<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins
let rs1 = 0;
let Inst{13-5} = opfval; // fp opcode
let Inst{4-3} = 0;
- let Inst{2-0} = siam_mode;
+ let Inst{2-0} = uimm3;
}
// Shift by register rs2.
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index 0e8f743a83d5b..d5af2000d0481 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -82,7 +82,8 @@ def UseDeprecatedInsts : Predicate<"Subtarget->useV8DeprecatedInsts()">;
// Instruction Pattern Stuff
//===----------------------------------------------------------------------===//
-def siam_mode : PatLeaf<(imm), [{ return isUInt<3>(N->getZExtValue()); }]>;
+// FIXME these should have AsmOperandClass.
+def uimm3 : PatLeaf<(imm), [{ return isUInt<3>(N->getZExtValue()); }]>;
def simm10 : PatLeaf<(imm), [{ return isInt<10>(N->getSExtValue()); }]>;
diff --git a/llvm/lib/Target/Sparc/SparcInstrVIS.td b/llvm/lib/Target/Sparc/SparcInstrVIS.td
index fbf56ae22cd30..ccdb724614b83 100644
--- a/llvm/lib/Target/Sparc/SparcInstrVIS.td
+++ b/llvm/lib/Target/Sparc/SparcInstrVIS.td
@@ -172,7 +172,7 @@ def BSHUFFLE : VISInst<0b001001100, "bshuffle">;
let rd = 0, rs1 = 0 in
def SIAM : F3_3_siam<0b10, 0b110110, 0b010000001, (outs),
- (ins i32imm:$siam_mode), "siam $siam_mode", []>;
+ (ins i32imm:$uimm3), "siam $uimm3", []>;
def EDGE8N : VISInst<0b000000001, "edge8n", I64Regs>;
def EDGE8LN : VISInst<0b000000011, "edge8ln", I64Regs>;
diff --git a/llvm/test/MC/Sparc/sparc-vis.s b/llvm/test/MC/Sparc/sparc-vis.s
index bed901b6a7272..771d036e32db5 100644
--- a/llvm/test/MC/Sparc/sparc-vis.s
+++ b/llvm/test/MC/Sparc/sparc-vis.s
@@ -1,4 +1,4 @@
-! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-VIS
+! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-VIS --implicit-check-not=error:
! RUN: llvm-mc %s -triple=sparcv9 -mattr=+vis -show-encoding | FileCheck %s --check-prefixes=VIS
!! VIS 1 instructions.
diff --git a/llvm/test/MC/Sparc/sparc-vis2.s b/llvm/test/MC/Sparc/sparc-vis2.s
index c025249ea4b93..3318884388562 100644
--- a/llvm/test/MC/Sparc/sparc-vis2.s
+++ b/llvm/test/MC/Sparc/sparc-vis2.s
@@ -1,5 +1,5 @@
! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-VIS2
-! RUN: llvm-mc %s -triple=sparcv9 -mattr=+vis2 -show-encoding | FileCheck %s --check-prefixes=VIS2
+! RUN: llvm-mc %s -triple=sparcv9 -mattr=+vis2 -show-encoding | FileCheck %s --check-prefixes=VIS2 --implicit-check-not=error:
!! VIS 2 instructions.
diff --git a/llvm/test/MC/Sparc/sparc-vis3.s b/llvm/test/MC/Sparc/sparc-vis3.s
index 14da013fd1f22..ea189fb344767 100644
--- a/llvm/test/MC/Sparc/sparc-vis3.s
+++ b/llvm/test/MC/Sparc/sparc-vis3.s
@@ -1,5 +1,5 @@
! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-VIS3
-! RUN: llvm-mc %s -triple=sparcv9 -mattr=+vis3 -show-encoding | FileCheck %s --check-prefixes=VIS3
+! RUN: llvm-mc %s -triple=sparcv9 -mattr=+vis3 -show-encoding | FileCheck %s --check-prefixes=VIS3 --implicit-check-not=error:
!! VIS 3 instructions.
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