[llvm-branch-commits] [llvm] [AMDGPU] Precommit si-fold-bitmask.mir (PR #131310)

[Pierre van Houtryve via llvm-branch-commits]

Pierre-vh wrote:

> > Where and how should that be implemented ? I struggled with that. I tried adding a new special case in TableGen but I just couldn't find the right way to do it. Do I just add it in C++ InstructionSelector before it checks the patterns? Or should it be some kind of post-processing step after the shift has been selected, but before the G_ZEXT is selected?
> 
> It already exists as a complex pattern, isUnneededShiftMask. The combiners should be trying to get the clamping code into this form which expects the and

I tried it but the DAG immediately transforms `(and x, 0xFF)` into a zext and it seems pretty stubborn about it as it's a basic transform.
I don't mind trying to make it work a bit longer, but I could also just bring this back. What do you think?

https://github.com/llvm/llvm-project/pull/131310