[llvm-branch-commits] [llvm] [AMDGPU] Support image_bvh8_intersect_ray instruction and intrinsic. (PR #130041)

[Mirko Brkušanin via llvm-branch-commits]

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@@ -1509,18 +1509,18 @@ multiclass MIMG_Gather <mimgopc op, AMDGPUSampleVariant sample, bit wqm = 0,
 multiclass MIMG_Gather_WQM <mimgopc op, AMDGPUSampleVariant sample>
     : MIMG_Gather<op, sample, 1>;
 
-class MIMG_IntersectRay_Helper<bit Is64, bit IsA16, bit isDual> {
-  int num_addrs = !if(Is64, !if(IsA16, 9, 12), !if(IsA16, 8, 11));
+class MIMG_IntersectRay_Helper<bit Is64, bit IsA16, bit isDual, bit isBVH8> {
+  int num_addrs = !if(isBVH8, 11, !if(Is64, !if(IsA16, 9, 12), !if(IsA16, 8, 11)));
   RegisterClass RegClass = MIMGAddrSize<num_addrs, 0>.RegClass;
   int VAddrDwords = !srl(RegClass.Size, 5);
 
   int GFX11PlusNSAAddrs = !if(IsA16, 4, 5);
   RegisterClass node_ptr_type = !if(Is64, VReg_64, VGPR_32);
   list<RegisterClass> GFX11PlusAddrTypes =
-    !if(isDual, [VReg_64, VReg_64, VReg_96, VReg_96, VReg_64],
-         !if(IsA16,
-              [node_ptr_type, VGPR_32, VReg_96, VReg_96],
-              [node_ptr_type, VGPR_32, VReg_96, VReg_96, VReg_96]));
+     !cond(!eq(isBVH8, 1) : [node_ptr_type, VReg_64, VReg_96, VReg_96, VGPR_32],
+           !eq(isDual, 1) : [node_ptr_type, VReg_64, VReg_96, VReg_96, VReg_64],
+           !eq(IsA16,  0) : [node_ptr_type, VGPR_32, VReg_96, VReg_96, VReg_96],
+           !eq(IsA16,  1) : [node_ptr_type, VGPR_32, VReg_96, VReg_96]);
----------------
mbrkusanin wrote:

```suggestion
     !cond(isBVH8 : [node_ptr_type, VReg_64, VReg_96, VReg_96, VGPR_32],
           isDual : [node_ptr_type, VReg_64, VReg_96, VReg_96, VReg_64],
           IsA16  : [node_ptr_type, VGPR_32, VReg_96, VReg_96],
           true   : [node_ptr_type, VGPR_32, VReg_96, VReg_96, VReg_96]);
```

!eq(X, 1) is redundant here, and last two options can be swapped

https://github.com/llvm/llvm-project/pull/130041