[llvm-branch-commits] [llvm] [GlobalISel] Combine redundant sext_inreg (PR #131624)

[Matt Arsenault via llvm-branch-commits]

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@@ -372,3 +372,30 @@ bool CombinerHelper::matchCastOfInteger(const MachineInstr &CastMI,
     return false;
   }
 }
+
+void CombinerHelper::applyRedundantSextInReg(MachineInstr &Root,
+                                             MachineInstr &Other) const {
+  assert(Root.getOpcode() == TargetOpcode::G_SEXT_INREG &&
+         Other.getOpcode() == TargetOpcode::G_SEXT_INREG);
+
+  unsigned RootWidth = Root.getOperand(2).getImm();
+  unsigned OtherWidth = Other.getOperand(2).getImm();
+
+  Register Dst = Root.getOperand(0).getReg();
+  Register OtherDst = Other.getOperand(0).getReg();
+  Register Src = Other.getOperand(1).getReg();
+
+  if (RootWidth >= OtherWidth) {
+    // The root sext_inreg is entirely redundant because the other one
+    // is narrower.
+    Observer.changingAllUsesOfReg(MRI, Dst);
+    MRI.replaceRegWith(Dst, OtherDst);
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arsenm wrote:

Missing canReplaceReg check? This could break after regbank 

https://github.com/llvm/llvm-project/pull/131624