[llvm-branch-commits] [llvm] [AMDGPU] Prevent SI_CS_CHAIN instruction from giving registers classes in generic instructions (PR #131329)

[Matt Arsenault via llvm-branch-commits]

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@@ -1278,7 +1278,11 @@ bool AMDGPUCallLowering::lowerTailCall(
       if (auto CI = dyn_cast<ConstantInt>(Arg.OrigValue)) {
         MIB.addImm(CI->getSExtValue());
       } else {
-        MIB.addReg(Arg.Regs[0]);
+        Register Reg = Arg.Regs[0];
+        if (!MRI.getVRegDef(Reg)->isCopy())
+          Reg = MIRBuilder.buildCopy(MRI.getType(Reg), Reg).getReg(0);
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arsenm wrote:

If you need to adjust the class, should use constrainOperandRegClass instead of special casing copy 

https://github.com/llvm/llvm-project/pull/131329