[llvm-branch-commits] [llvm] [AMDGPU][GlobalISel] Allow forming s16 U/SBFX pre-regbankselect (PR #131309)
Pierre van Houtryve via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Mar 14 04:29:59 PDT 2025
https://github.com/Pierre-vh updated https://github.com/llvm/llvm-project/pull/131309
>From c30cc50e3650137bdb8acc9674c312f6c088983f Mon Sep 17 00:00:00 2001
From: pvanhout <pierre.vanhoutryve at amd.com>
Date: Wed, 12 Mar 2025 09:43:15 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Allow forming s16 U/SBFX
pre-regbankselect
Make s16 G_U/SBFX legal and widen them in RegBankSelect.
This allows the set of BFX formation combines to work on s16 types.
---
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 9 +-
.../Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 33 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll | 645 ++++++++----------
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll | 380 ++++-------
.../AMDGPU/GlobalISel/legalize-sbfx.mir | 26 +-
.../AMDGPU/GlobalISel/legalize-ubfx.mir | 27 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll | 27 +-
7 files changed, 503 insertions(+), 644 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index cfb5c3b3006f0..ab900157d2095 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2069,10 +2069,13 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.minScalar(0, S32)
.lower();
+ // Only {S32, S32} or {S32, S64} should ever reach codegen.
+ // We allow S/UBFX for S16 so the combiner can form them before
+ // RegBankSelect, and RegBankSelect will then legalize them correctly.
getActionDefinitionsBuilder({G_SBFX, G_UBFX})
- .legalFor({{S32, S32}, {S64, S32}})
- .clampScalar(1, S32, S32)
- .clampScalar(0, S32, S64)
+ .legalFor({{S16, S16}, {S32, S32}, {S64, S32}})
+ .clampScalar(1, S16, S32)
+ .clampScalar(0, S16, S64)
.widenScalarToNextPow2(0)
.scalarize(0);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 27b86723ce474..ed0d52f6b2441 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -1485,7 +1485,9 @@ bool AMDGPURegisterBankInfo::applyMappingBFE(MachineIRBuilder &B,
Register DstReg = MI.getOperand(0).getReg();
LLT Ty = MRI.getType(DstReg);
+ const LLT S64 = LLT::scalar(64);
const LLT S32 = LLT::scalar(32);
+ const LLT S16 = LLT::scalar(16);
unsigned FirstOpnd = isa<GIntrinsic>(MI) ? 2 : 1;
Register SrcReg = MI.getOperand(FirstOpnd).getReg();
@@ -1495,6 +1497,18 @@ bool AMDGPURegisterBankInfo::applyMappingBFE(MachineIRBuilder &B,
const RegisterBank *DstBank =
OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
if (DstBank == &AMDGPU::VGPRRegBank) {
+ if (Ty == S16) {
+ ApplyRegBankMapping ApplyBank(B, *this, MRI, &AMDGPU::VGPRRegBank);
+ B.setInsertPt(B.getMBB(), MI);
+ LegalizerHelper Helper(B.getMF(), ApplyBank, B);
+
+ Helper.widenScalarDst(MI, S32);
+ Helper.widenScalarSrc(MI, S32, 1, AMDGPU::G_ANYEXT);
+ Helper.widenScalarSrc(MI, S32, 2, AMDGPU::G_ZEXT);
+ Helper.widenScalarSrc(MI, S32, 3, AMDGPU::G_ZEXT);
+ return true;
+ }
+
if (Ty == S32)
return true;
@@ -1554,6 +1568,11 @@ bool AMDGPURegisterBankInfo::applyMappingBFE(MachineIRBuilder &B,
ApplyRegBankMapping ApplyBank(B, *this, MRI, &AMDGPU::SGPRRegBank);
+ if (Ty == S16) {
+ OffsetReg = B.buildAnyExtOrTrunc(S32, OffsetReg).getReg(0);
+ WidthReg = B.buildAnyExtOrTrunc(S32, WidthReg).getReg(0);
+ }
+
// Ensure the high bits are clear to insert the offset.
auto OffsetMask = B.buildConstant(S32, maskTrailingOnes<unsigned>(6));
auto ClampOffset = B.buildAnd(S32, OffsetReg, OffsetMask);
@@ -1568,13 +1587,21 @@ bool AMDGPURegisterBankInfo::applyMappingBFE(MachineIRBuilder &B,
// TODO: It might be worth using a pseudo here to avoid scc clobber and
// register class constraints.
- unsigned Opc = Ty == S32 ? (Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32) :
- (Signed ? AMDGPU::S_BFE_I64 : AMDGPU::S_BFE_U64);
+ unsigned Opc = (Ty != S64) ? (Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32)
+ : (Signed ? AMDGPU::S_BFE_I64 : AMDGPU::S_BFE_U64);
- auto MIB = B.buildInstr(Opc, {DstReg}, {SrcReg, MergedInputs});
+ Register BFEDst = DstReg;
+ if (Ty == S16) {
+ BFEDst = MRI.createGenericVirtualRegister(S32);
+ MRI.setRegBank(BFEDst, AMDGPU::SGPRRegBank);
+ }
+ auto MIB = B.buildInstr(Opc, {BFEDst}, {SrcReg, MergedInputs});
if (!constrainSelectedInstRegOperands(*MIB, *TII, *TRI, *this))
llvm_unreachable("failed to constrain BFE");
+ if (BFEDst != DstReg)
+ B.buildZExtOrTrunc(DstReg, BFEDst);
+
MI.eraseFromParent();
return true;
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
index 07fcb02d98649..d2b600b04f9fc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -40,8 +40,7 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX8-NEXT: s_and_b32 s1, s1, 0x7f
-; GFX8-NEXT: s_lshr_b32 s1, s1, 1
+; GFX8-NEXT: s_bfe_u32 s1, s1, 0x60001
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: v_mul_lo_u32 v1, v0, -7
@@ -70,8 +69,7 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX9-NEXT: s_and_b32 s1, s1, 0x7f
-; GFX9-NEXT: s_lshr_b32 s1, s1, 1
+; GFX9-NEXT: s_bfe_u32 s1, s1, 0x60001
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_lo_u32 v1, v0, -7
@@ -99,8 +97,7 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
; GFX10-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX10-NEXT: s_and_b32 s1, s1, 0x7f
-; GFX10-NEXT: s_lshr_b32 s1, s1, 1
+; GFX10-NEXT: s_bfe_u32 s1, s1, 0x60001
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
@@ -129,40 +126,38 @@ define amdgpu_ps i7 @s_fshl_i7(i7 inreg %lhs, i7 inreg %rhs, i7 inreg %amt) {
; GFX11: ; %bb.0:
; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, 7
; GFX11-NEXT: s_and_b32 s2, s2, 0x7f
-; GFX11-NEXT: s_and_b32 s1, s1, 0x7f
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: s_lshr_b32 s1, s1, 1
+; GFX11-NEXT: s_bfe_u32 s1, s1, 0x60001
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-NEXT: v_mul_lo_u32 v1, v0, -7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_lo_u32 v1, v0, -7
; GFX11-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v0, v0, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v0, v0, v1
; GFX11-NEXT: v_mul_hi_u32 v0, s2, v0
-; GFX11-NEXT: v_mul_lo_u32 v0, v0, 7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_lo_u32 v0, v0, 7
; GFX11-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_nc_u32_e32 v1, -7, v0
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_nc_u32_e32 v1, -7, v0
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_sub_nc_u16 v1, 6, v0
; GFX11-NEXT: v_and_b32_e32 v0, 0x7f, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_b32_e32 v1, 0x7f, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshlrev_b16 v0, v0, s0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshrrev_b16 v1, v1, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: ; return to shader part epilog
%result = call i7 @llvm.fshl.i7(i7 %lhs, i7 %rhs, i7 %amt)
@@ -205,8 +200,7 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v2
-; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v1
-; GFX8-NEXT: v_lshrrev_b16_e32 v1, 1, v1
+; GFX8-NEXT: v_bfe_u32 v1, v1, 1, 6
; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX8-NEXT: v_mul_lo_u32 v4, v3, -7
@@ -235,8 +229,7 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX9-NEXT: v_and_b32_e32 v2, 0x7f, v2
-; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v1
-; GFX9-NEXT: v_lshrrev_b16_e32 v1, 1, v1
+; GFX9-NEXT: v_bfe_u32 v1, v1, 1, 6
; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX9-NEXT: v_mul_lo_u32 v4, v3, -7
@@ -264,9 +257,8 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
; GFX10-NEXT: v_and_b32_e32 v2, 0x7f, v2
-; GFX10-NEXT: v_and_b32_e32 v1, 0x7f, v1
+; GFX10-NEXT: v_bfe_u32 v1, v1, 1, 6
; GFX10-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX10-NEXT: v_lshrrev_b16 v1, 1, v1
; GFX10-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX10-NEXT: v_mul_lo_u32 v4, v3, -7
@@ -294,38 +286,37 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
; GFX11-NEXT: v_and_b32_e32 v2, 0x7f, v2
-; GFX11-NEXT: v_and_b32_e32 v1, 0x7f, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_bfe_u32 v1, v1, 1, 6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX11-NEXT: v_lshrrev_b16 v1, 1, v1
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX11-NEXT: v_mul_lo_u32 v4, v3, -7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_lo_u32 v4, v3, -7
; GFX11-NEXT: v_mul_hi_u32 v4, v3, v4
-; GFX11-NEXT: v_add_nc_u32_e32 v3, v3, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v3, v3, v4
; GFX11-NEXT: v_mul_hi_u32 v3, v2, v3
-; GFX11-NEXT: v_mul_lo_u32 v3, v3, 7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_lo_u32 v3, v3, 7
; GFX11-NEXT: v_sub_nc_u32_e32 v2, v2, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_nc_u32_e32 v3, -7, v2
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_nc_u32_e32 v3, -7, v2
; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_sub_nc_u16 v3, 6, v2
; GFX11-NEXT: v_and_b32_e32 v2, 0x7f, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_b32_e32 v3, 0x7f, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshlrev_b16 v0, v2, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshrrev_b16 v1, v3, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i7 @llvm.fshl.i7(i7 %lhs, i7 %rhs, i7 %amt)
@@ -345,10 +336,10 @@ define amdgpu_ps i8 @s_fshl_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
;
; GFX8-LABEL: s_fshl_i8:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_and_b32 s1, s1, 0xff
+; GFX8-NEXT: s_bfe_u32 s1, s1, 0x70001
; GFX8-NEXT: s_and_b32 s3, s2, 7
-; GFX8-NEXT: s_lshr_b32 s1, s1, 1
; GFX8-NEXT: s_andn2_b32 s2, 7, s2
+; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_lshl_b32 s0, s0, s3
; GFX8-NEXT: s_lshr_b32 s1, s1, s2
; GFX8-NEXT: s_or_b32 s0, s0, s1
@@ -356,10 +347,10 @@ define amdgpu_ps i8 @s_fshl_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
;
; GFX9-LABEL: s_fshl_i8:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_and_b32 s1, s1, 0xff
+; GFX9-NEXT: s_bfe_u32 s1, s1, 0x70001
; GFX9-NEXT: s_and_b32 s3, s2, 7
-; GFX9-NEXT: s_lshr_b32 s1, s1, 1
; GFX9-NEXT: s_andn2_b32 s2, 7, s2
+; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, s3
; GFX9-NEXT: s_lshr_b32 s1, s1, s2
; GFX9-NEXT: s_or_b32 s0, s0, s1
@@ -367,10 +358,10 @@ define amdgpu_ps i8 @s_fshl_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
;
; GFX10-LABEL: s_fshl_i8:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_and_b32 s1, s1, 0xff
+; GFX10-NEXT: s_bfe_u32 s1, s1, 0x70001
; GFX10-NEXT: s_and_b32 s3, s2, 7
-; GFX10-NEXT: s_lshr_b32 s1, s1, 1
; GFX10-NEXT: s_andn2_b32 s2, 7, s2
+; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
; GFX10-NEXT: s_lshl_b32 s0, s0, s3
; GFX10-NEXT: s_lshr_b32 s1, s1, s2
; GFX10-NEXT: s_or_b32 s0, s0, s1
@@ -378,10 +369,10 @@ define amdgpu_ps i8 @s_fshl_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
;
; GFX11-LABEL: s_fshl_i8:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_bfe_u32 s1, s1, 0x70001
; GFX11-NEXT: s_and_b32 s3, s2, 7
-; GFX11-NEXT: s_lshr_b32 s1, s1, 1
; GFX11-NEXT: s_and_not1_b32 s2, 7, s2
+; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
; GFX11-NEXT: s_lshl_b32 s0, s0, s3
; GFX11-NEXT: s_lshr_b32 s1, s1, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -408,11 +399,10 @@ define i8 @v_fshl_i8(i8 %lhs, i8 %rhs, i8 %amt) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_and_b32_e32 v3, 7, v2
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, v3, v0
-; GFX8-NEXT: v_mov_b32_e32 v3, 1
; GFX8-NEXT: v_xor_b32_e32 v2, -1, v2
-; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_bfe_u32 v1, v1, 1, 7
; GFX8-NEXT: v_and_b32_e32 v2, 7, v2
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, v3, v0
; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -421,11 +411,10 @@ define i8 @v_fshl_i8(i8 %lhs, i8 %rhs, i8 %amt) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v3, 7, v2
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, v3, v0
-; GFX9-NEXT: v_mov_b32_e32 v3, 1
; GFX9-NEXT: v_xor_b32_e32 v2, -1, v2
-; GFX9-NEXT: v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_bfe_u32 v1, v1, 1, 7
; GFX9-NEXT: v_and_b32_e32 v2, 7, v2
+; GFX9-NEXT: v_lshlrev_b16_e32 v0, v3, v0
; GFX9-NEXT: v_lshrrev_b16_e32 v1, v2, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -433,10 +422,9 @@ define i8 @v_fshl_i8(i8 %lhs, i8 %rhs, i8 %amt) {
; GFX10-LABEL: v_fshl_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-NEXT: v_xor_b32_e32 v3, -1, v2
; GFX10-NEXT: v_and_b32_e32 v2, 7, v2
-; GFX10-NEXT: v_lshrrev_b16 v1, 1, v1
+; GFX10-NEXT: v_bfe_u32 v1, v1, 1, 7
; GFX10-NEXT: v_and_b32_e32 v3, 7, v3
; GFX10-NEXT: v_lshlrev_b16 v0, v2, v0
; GFX10-NEXT: v_lshrrev_b16 v1, v3, v1
@@ -446,16 +434,14 @@ define i8 @v_fshl_i8(i8 %lhs, i8 %rhs, i8 %amt) {
; GFX11-LABEL: v_fshl_i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_xor_b32_e32 v3, -1, v2
; GFX11-NEXT: v_and_b32_e32 v2, 7, v2
+; GFX11-NEXT: v_bfe_u32 v1, v1, 1, 7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshrrev_b16 v1, 1, v1
; GFX11-NEXT: v_and_b32_e32 v3, 7, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshlrev_b16 v0, v2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshrrev_b16 v1, v3, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.fshl.i8(i8 %lhs, i8 %rhs, i8 %amt)
@@ -463,42 +449,17 @@ define i8 @v_fshl_i8(i8 %lhs, i8 %rhs, i8 %amt) {
}
define amdgpu_ps i8 @s_fshl_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
-; GFX6-LABEL: s_fshl_i8_4:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshl_b32 s0, s0, 4
-; GFX6-NEXT: s_bfe_u32 s1, s1, 0x40004
-; GFX6-NEXT: s_or_b32 s0, s0, s1
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshl_i8_4:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_and_b32 s1, s1, 0xff
-; GFX8-NEXT: s_lshl_b32 s0, s0, 4
-; GFX8-NEXT: s_lshr_b32 s1, s1, 4
-; GFX8-NEXT: s_or_b32 s0, s0, s1
-; GFX8-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: s_fshl_i8_4:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_and_b32 s1, s1, 0xff
-; GFX9-NEXT: s_lshl_b32 s0, s0, 4
-; GFX9-NEXT: s_lshr_b32 s1, s1, 4
-; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: ; return to shader part epilog
-;
-; GFX10-LABEL: s_fshl_i8_4:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_and_b32 s1, s1, 0xff
-; GFX10-NEXT: s_lshl_b32 s0, s0, 4
-; GFX10-NEXT: s_lshr_b32 s1, s1, 4
-; GFX10-NEXT: s_or_b32 s0, s0, s1
-; GFX10-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshl_i8_4:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_lshl_b32 s0, s0, 4
+; GCN-NEXT: s_bfe_u32 s1, s1, 0x40004
+; GCN-NEXT: s_or_b32 s0, s0, s1
+; GCN-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_fshl_i8_4:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_lshl_b32 s0, s0, 4
-; GFX11-NEXT: s_lshr_b32 s1, s1, 4
+; GFX11-NEXT: s_bfe_u32 s1, s1, 0x40004
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_or_b32 s0, s0, s1
; GFX11-NEXT: ; return to shader part epilog
@@ -518,37 +479,33 @@ define i8 @v_fshl_i8_4(i8 %lhs, i8 %rhs) {
; GFX8-LABEL: v_fshl_i8_4:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v2, 4
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 4, v0
-; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_bfe_u32 v1, v1, 4, 4
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshl_i8_4:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v2, 4
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 4, v0
-; GFX9-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_bfe_u32 v1, v1, 4, 4
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fshl_i8_4:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-NEXT: v_lshlrev_b16 v0, 4, v0
-; GFX10-NEXT: v_lshrrev_b16 v1, 4, v1
+; GFX10-NEXT: v_bfe_u32 v1, v1, 4, 4
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fshl_i8_4:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_lshlrev_b16 v0, 4, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b16 v1, 4, v1
+; GFX11-NEXT: v_bfe_u32 v1, v1, 4, 4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.fshl.i8(i8 %lhs, i8 %rhs, i8 4)
@@ -556,42 +513,17 @@ define i8 @v_fshl_i8_4(i8 %lhs, i8 %rhs) {
}
define amdgpu_ps i8 @s_fshl_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
-; GFX6-LABEL: s_fshl_i8_5:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshl_b32 s0, s0, 5
-; GFX6-NEXT: s_bfe_u32 s1, s1, 0x50003
-; GFX6-NEXT: s_or_b32 s0, s0, s1
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshl_i8_5:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_and_b32 s1, s1, 0xff
-; GFX8-NEXT: s_lshl_b32 s0, s0, 5
-; GFX8-NEXT: s_lshr_b32 s1, s1, 3
-; GFX8-NEXT: s_or_b32 s0, s0, s1
-; GFX8-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: s_fshl_i8_5:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_and_b32 s1, s1, 0xff
-; GFX9-NEXT: s_lshl_b32 s0, s0, 5
-; GFX9-NEXT: s_lshr_b32 s1, s1, 3
-; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: ; return to shader part epilog
-;
-; GFX10-LABEL: s_fshl_i8_5:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_and_b32 s1, s1, 0xff
-; GFX10-NEXT: s_lshl_b32 s0, s0, 5
-; GFX10-NEXT: s_lshr_b32 s1, s1, 3
-; GFX10-NEXT: s_or_b32 s0, s0, s1
-; GFX10-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshl_i8_5:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_lshl_b32 s0, s0, 5
+; GCN-NEXT: s_bfe_u32 s1, s1, 0x50003
+; GCN-NEXT: s_or_b32 s0, s0, s1
+; GCN-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_fshl_i8_5:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_lshl_b32 s0, s0, 5
-; GFX11-NEXT: s_lshr_b32 s1, s1, 3
+; GFX11-NEXT: s_bfe_u32 s1, s1, 0x50003
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_or_b32 s0, s0, s1
; GFX11-NEXT: ; return to shader part epilog
@@ -611,37 +543,33 @@ define i8 @v_fshl_i8_5(i8 %lhs, i8 %rhs) {
; GFX8-LABEL: v_fshl_i8_5:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v2, 3
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 5, v0
-; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_bfe_u32 v1, v1, 3, 5
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshl_i8_5:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v2, 3
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 5, v0
-; GFX9-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_bfe_u32 v1, v1, 3, 5
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fshl_i8_5:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-NEXT: v_lshlrev_b16 v0, 5, v0
-; GFX10-NEXT: v_lshrrev_b16 v1, 3, v1
+; GFX10-NEXT: v_bfe_u32 v1, v1, 3, 5
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fshl_i8_5:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_lshlrev_b16 v0, 5, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b16 v1, 3, v1
+; GFX11-NEXT: v_bfe_u32 v1, v1, 3, 5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.fshl.i8(i8 %lhs, i8 %rhs, i8 5)
@@ -675,20 +603,20 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX8-LABEL: s_fshl_v2i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s4, s1, 8
-; GFX8-NEXT: s_and_b32 s1, s1, 0xff
+; GFX8-NEXT: s_bfe_u32 s1, s1, 0x70001
; GFX8-NEXT: s_lshr_b32 s5, s2, 8
; GFX8-NEXT: s_and_b32 s6, s2, 7
-; GFX8-NEXT: s_lshr_b32 s1, s1, 1
; GFX8-NEXT: s_andn2_b32 s2, 7, s2
+; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_lshr_b32 s3, s0, 8
; GFX8-NEXT: s_lshl_b32 s0, s0, s6
; GFX8-NEXT: s_lshr_b32 s1, s1, s2
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: s_and_b32 s1, s5, 7
-; GFX8-NEXT: s_and_b32 s2, s4, 0xff
+; GFX8-NEXT: s_bfe_u32 s2, s4, 0x70001
; GFX8-NEXT: s_lshl_b32 s1, s3, s1
-; GFX8-NEXT: s_lshr_b32 s2, s2, 1
; GFX8-NEXT: s_andn2_b32 s3, 7, s5
+; GFX8-NEXT: s_and_b32 s2, 0xffff, s2
; GFX8-NEXT: s_lshr_b32 s2, s2, s3
; GFX8-NEXT: s_or_b32 s1, s1, s2
; GFX8-NEXT: s_and_b32 s1, s1, 0xff
@@ -700,20 +628,20 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX9-LABEL: s_fshl_v2i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshr_b32 s4, s1, 8
-; GFX9-NEXT: s_and_b32 s1, s1, 0xff
+; GFX9-NEXT: s_bfe_u32 s1, s1, 0x70001
; GFX9-NEXT: s_lshr_b32 s5, s2, 8
; GFX9-NEXT: s_and_b32 s6, s2, 7
-; GFX9-NEXT: s_lshr_b32 s1, s1, 1
; GFX9-NEXT: s_andn2_b32 s2, 7, s2
+; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshr_b32 s3, s0, 8
; GFX9-NEXT: s_lshl_b32 s0, s0, s6
; GFX9-NEXT: s_lshr_b32 s1, s1, s2
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: s_and_b32 s1, s5, 7
-; GFX9-NEXT: s_and_b32 s2, s4, 0xff
+; GFX9-NEXT: s_bfe_u32 s2, s4, 0x70001
; GFX9-NEXT: s_lshl_b32 s1, s3, s1
-; GFX9-NEXT: s_lshr_b32 s2, s2, 1
; GFX9-NEXT: s_andn2_b32 s3, 7, s5
+; GFX9-NEXT: s_and_b32 s2, 0xffff, s2
; GFX9-NEXT: s_lshr_b32 s2, s2, s3
; GFX9-NEXT: s_or_b32 s1, s1, s2
; GFX9-NEXT: s_and_b32 s1, s1, 0xff
@@ -725,19 +653,19 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX10-LABEL: s_fshl_v2i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s4, s1, 8
-; GFX10-NEXT: s_lshr_b32 s5, s2, 8
-; GFX10-NEXT: s_and_b32 s6, s2, 7
-; GFX10-NEXT: s_and_b32 s4, s4, 0xff
+; GFX10-NEXT: s_and_b32 s5, s2, 7
+; GFX10-NEXT: s_lshr_b32 s6, s2, 8
+; GFX10-NEXT: s_bfe_u32 s4, s4, 0x70001
; GFX10-NEXT: s_lshr_b32 s3, s0, 8
-; GFX10-NEXT: s_and_b32 s1, s1, 0xff
-; GFX10-NEXT: s_lshl_b32 s0, s0, s6
-; GFX10-NEXT: s_and_b32 s6, s5, 7
-; GFX10-NEXT: s_lshr_b32 s4, s4, 1
-; GFX10-NEXT: s_andn2_b32 s5, 7, s5
-; GFX10-NEXT: s_lshr_b32 s1, s1, 1
+; GFX10-NEXT: s_lshl_b32 s0, s0, s5
+; GFX10-NEXT: s_bfe_u32 s1, s1, 0x70001
+; GFX10-NEXT: s_and_b32 s5, s6, 7
+; GFX10-NEXT: s_andn2_b32 s6, 7, s6
+; GFX10-NEXT: s_and_b32 s4, 0xffff, s4
; GFX10-NEXT: s_andn2_b32 s2, 7, s2
-; GFX10-NEXT: s_lshl_b32 s3, s3, s6
-; GFX10-NEXT: s_lshr_b32 s4, s4, s5
+; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX10-NEXT: s_lshl_b32 s3, s3, s5
+; GFX10-NEXT: s_lshr_b32 s4, s4, s6
; GFX10-NEXT: s_lshr_b32 s1, s1, s2
; GFX10-NEXT: s_or_b32 s2, s3, s4
; GFX10-NEXT: s_or_b32 s0, s0, s1
@@ -750,19 +678,19 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX11-LABEL: s_fshl_v2i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_lshr_b32 s4, s1, 8
-; GFX11-NEXT: s_lshr_b32 s5, s2, 8
-; GFX11-NEXT: s_and_b32 s6, s2, 7
-; GFX11-NEXT: s_and_b32 s4, s4, 0xff
+; GFX11-NEXT: s_and_b32 s5, s2, 7
+; GFX11-NEXT: s_lshr_b32 s6, s2, 8
+; GFX11-NEXT: s_bfe_u32 s4, s4, 0x70001
; GFX11-NEXT: s_lshr_b32 s3, s0, 8
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-NEXT: s_lshl_b32 s0, s0, s6
-; GFX11-NEXT: s_and_b32 s6, s5, 7
-; GFX11-NEXT: s_lshr_b32 s4, s4, 1
-; GFX11-NEXT: s_and_not1_b32 s5, 7, s5
-; GFX11-NEXT: s_lshr_b32 s1, s1, 1
+; GFX11-NEXT: s_lshl_b32 s0, s0, s5
+; GFX11-NEXT: s_bfe_u32 s1, s1, 0x70001
+; GFX11-NEXT: s_and_b32 s5, s6, 7
+; GFX11-NEXT: s_and_not1_b32 s6, 7, s6
+; GFX11-NEXT: s_and_b32 s4, 0xffff, s4
; GFX11-NEXT: s_and_not1_b32 s2, 7, s2
-; GFX11-NEXT: s_lshl_b32 s3, s3, s6
-; GFX11-NEXT: s_lshr_b32 s4, s4, s5
+; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX11-NEXT: s_lshl_b32 s3, s3, s5
+; GFX11-NEXT: s_lshr_b32 s4, s4, s6
; GFX11-NEXT: s_lshr_b32 s1, s1, s2
; GFX11-NEXT: s_or_b32 s2, s3, s4
; GFX11-NEXT: s_or_b32 s0, s0, s1
@@ -810,21 +738,20 @@ define i16 @v_fshl_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
; GFX8-LABEL: v_fshl_v2i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v6, 7, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 8, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 8, v2
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, v6, v0
-; GFX8-NEXT: v_mov_b32_e32 v6, 1
+; GFX8-NEXT: v_and_b32_e32 v6, 7, v2
; GFX8-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 8, v1
-; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_bfe_u32 v1, v1, 1, 7
; GFX8-NEXT: v_and_b32_e32 v2, 7, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 8, v0
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, v6, v0
; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_and_b32_e32 v1, 7, v5
; GFX8-NEXT: v_lshlrev_b16_e32 v1, v1, v3
; GFX8-NEXT: v_xor_b32_e32 v3, -1, v5
-; GFX8-NEXT: v_lshrrev_b16_sdwa v2, v6, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_bfe_u32 v2, v4, 1, 7
; GFX8-NEXT: v_and_b32_e32 v3, 7, v3
; GFX8-NEXT: v_lshrrev_b16_e32 v2, v3, v2
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
@@ -836,21 +763,20 @@ define i16 @v_fshl_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
; GFX9-LABEL: v_fshl_v2i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v6, 7, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v2
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, v6, v0
-; GFX9-NEXT: v_mov_b32_e32 v6, 1
+; GFX9-NEXT: v_and_b32_e32 v6, 7, v2
; GFX9-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 8, v1
-; GFX9-NEXT: v_lshrrev_b16_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_bfe_u32 v1, v1, 1, 7
; GFX9-NEXT: v_and_b32_e32 v2, 7, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v0
+; GFX9-NEXT: v_lshlrev_b16_e32 v0, v6, v0
; GFX9-NEXT: v_lshrrev_b16_e32 v1, v2, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_and_b32_e32 v1, 7, v5
; GFX9-NEXT: v_lshlrev_b16_e32 v1, v1, v3
; GFX9-NEXT: v_xor_b32_e32 v3, -1, v5
-; GFX9-NEXT: v_lshrrev_b16_sdwa v2, v6, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_bfe_u32 v2, v4, 1, 7
; GFX9-NEXT: v_and_b32_e32 v3, 7, v3
; GFX9-NEXT: v_lshrrev_b16_e32 v2, v3, v2
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
@@ -862,26 +788,24 @@ define i16 @v_fshl_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
; GFX10-LABEL: v_fshl_v2i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshrrev_b32_e32 v3, 8, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v4, 8, v2
-; GFX10-NEXT: v_lshrrev_b32_e32 v5, 8, v0
-; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX10-NEXT: v_lshrrev_b32_e32 v3, 8, v2
+; GFX10-NEXT: v_lshrrev_b32_e32 v4, 8, v1
+; GFX10-NEXT: v_lshrrev_b32_e32 v6, 8, v0
; GFX10-NEXT: v_xor_b32_e32 v7, -1, v2
-; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX10-NEXT: v_xor_b32_e32 v6, -1, v4
-; GFX10-NEXT: v_and_b32_e32 v4, 7, v4
; GFX10-NEXT: v_and_b32_e32 v2, 7, v2
-; GFX10-NEXT: v_lshrrev_b16 v1, 1, v1
-; GFX10-NEXT: v_lshrrev_b16 v3, 1, v3
-; GFX10-NEXT: v_and_b32_e32 v6, 7, v6
+; GFX10-NEXT: v_xor_b32_e32 v5, -1, v3
+; GFX10-NEXT: v_and_b32_e32 v3, 7, v3
+; GFX10-NEXT: v_bfe_u32 v4, v4, 1, 7
+; GFX10-NEXT: v_bfe_u32 v1, v1, 1, 7
; GFX10-NEXT: v_and_b32_e32 v7, 7, v7
-; GFX10-NEXT: v_lshlrev_b16 v4, v4, v5
+; GFX10-NEXT: v_and_b32_e32 v5, 7, v5
+; GFX10-NEXT: v_lshlrev_b16 v3, v3, v6
; GFX10-NEXT: v_lshlrev_b16 v0, v2, v0
-; GFX10-NEXT: v_lshrrev_b16 v3, v6, v3
; GFX10-NEXT: v_lshrrev_b16 v1, v7, v1
-; GFX10-NEXT: v_or_b32_e32 v2, v4, v3
-; GFX10-NEXT: v_mov_b32_e32 v3, 0xff
+; GFX10-NEXT: v_lshrrev_b16 v4, v5, v4
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX10-NEXT: v_or_b32_e32 v2, v3, v4
+; GFX10-NEXT: v_mov_b32_e32 v3, 0xff
; GFX10-NEXT: v_and_b32_sdwa v1, v2, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -889,31 +813,29 @@ define i16 @v_fshl_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
; GFX11-LABEL: v_fshl_v2i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v4, 8, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v0
-; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v4, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v6, 8, v0
; GFX11-NEXT: v_xor_b32_e32 v7, -1, v2
-; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-NEXT: v_xor_b32_e32 v6, -1, v4
-; GFX11-NEXT: v_and_b32_e32 v4, 7, v4
; GFX11-NEXT: v_and_b32_e32 v2, 7, v2
-; GFX11-NEXT: v_lshrrev_b16 v1, 1, v1
-; GFX11-NEXT: v_lshrrev_b16 v3, 1, v3
-; GFX11-NEXT: v_and_b32_e32 v6, 7, v6
+; GFX11-NEXT: v_xor_b32_e32 v5, -1, v3
+; GFX11-NEXT: v_and_b32_e32 v3, 7, v3
+; GFX11-NEXT: v_bfe_u32 v4, v4, 1, 7
+; GFX11-NEXT: v_bfe_u32 v1, v1, 1, 7
; GFX11-NEXT: v_and_b32_e32 v7, 7, v7
-; GFX11-NEXT: v_lshlrev_b16 v4, v4, v5
+; GFX11-NEXT: v_and_b32_e32 v5, 7, v5
+; GFX11-NEXT: v_lshlrev_b16 v3, v3, v6
; GFX11-NEXT: v_lshlrev_b16 v0, v2, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshrrev_b16 v3, v6, v3
; GFX11-NEXT: v_lshrrev_b16 v1, v7, v1
+; GFX11-NEXT: v_lshrrev_b16 v4, v5, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v3
; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_or_b32_e32 v2, v3, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b16 v1, 8, v1
; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -977,13 +899,13 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX8-NEXT: s_lshr_b32 s6, s1, 8
; GFX8-NEXT: s_lshr_b32 s7, s1, 16
; GFX8-NEXT: s_lshr_b32 s8, s1, 24
-; GFX8-NEXT: s_and_b32 s1, s1, 0xff
+; GFX8-NEXT: s_bfe_u32 s1, s1, 0x70001
; GFX8-NEXT: s_lshr_b32 s9, s2, 8
; GFX8-NEXT: s_lshr_b32 s10, s2, 16
; GFX8-NEXT: s_lshr_b32 s11, s2, 24
; GFX8-NEXT: s_and_b32 s12, s2, 7
-; GFX8-NEXT: s_lshr_b32 s1, s1, 1
; GFX8-NEXT: s_andn2_b32 s2, 7, s2
+; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_lshr_b32 s3, s0, 8
; GFX8-NEXT: s_lshr_b32 s4, s0, 16
; GFX8-NEXT: s_lshr_b32 s5, s0, 24
@@ -991,17 +913,17 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX8-NEXT: s_lshr_b32 s1, s1, s2
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: s_and_b32 s1, s9, 7
-; GFX8-NEXT: s_and_b32 s2, s6, 0xff
+; GFX8-NEXT: s_bfe_u32 s2, s6, 0x70001
; GFX8-NEXT: s_lshl_b32 s1, s3, s1
-; GFX8-NEXT: s_lshr_b32 s2, s2, 1
; GFX8-NEXT: s_andn2_b32 s3, 7, s9
+; GFX8-NEXT: s_and_b32 s2, 0xffff, s2
; GFX8-NEXT: s_lshr_b32 s2, s2, s3
; GFX8-NEXT: s_or_b32 s1, s1, s2
; GFX8-NEXT: s_and_b32 s2, s10, 7
-; GFX8-NEXT: s_and_b32 s3, s7, 0xff
+; GFX8-NEXT: s_bfe_u32 s3, s7, 0x70001
; GFX8-NEXT: s_lshl_b32 s2, s4, s2
-; GFX8-NEXT: s_lshr_b32 s3, s3, 1
; GFX8-NEXT: s_andn2_b32 s4, 7, s10
+; GFX8-NEXT: s_and_b32 s3, 0xffff, s3
; GFX8-NEXT: s_lshr_b32 s3, s3, s4
; GFX8-NEXT: s_or_b32 s2, s2, s3
; GFX8-NEXT: s_and_b32 s3, s11, 7
@@ -1027,13 +949,13 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX9-NEXT: s_lshr_b32 s6, s1, 8
; GFX9-NEXT: s_lshr_b32 s7, s1, 16
; GFX9-NEXT: s_lshr_b32 s8, s1, 24
-; GFX9-NEXT: s_and_b32 s1, s1, 0xff
+; GFX9-NEXT: s_bfe_u32 s1, s1, 0x70001
; GFX9-NEXT: s_lshr_b32 s9, s2, 8
; GFX9-NEXT: s_lshr_b32 s10, s2, 16
; GFX9-NEXT: s_lshr_b32 s11, s2, 24
; GFX9-NEXT: s_and_b32 s12, s2, 7
-; GFX9-NEXT: s_lshr_b32 s1, s1, 1
; GFX9-NEXT: s_andn2_b32 s2, 7, s2
+; GFX9-NEXT: s_and_b32 s1, 0xffff, s1
; GFX9-NEXT: s_lshr_b32 s3, s0, 8
; GFX9-NEXT: s_lshr_b32 s4, s0, 16
; GFX9-NEXT: s_lshr_b32 s5, s0, 24
@@ -1041,17 +963,17 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX9-NEXT: s_lshr_b32 s1, s1, s2
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: s_and_b32 s1, s9, 7
-; GFX9-NEXT: s_and_b32 s2, s6, 0xff
+; GFX9-NEXT: s_bfe_u32 s2, s6, 0x70001
; GFX9-NEXT: s_lshl_b32 s1, s3, s1
-; GFX9-NEXT: s_lshr_b32 s2, s2, 1
; GFX9-NEXT: s_andn2_b32 s3, 7, s9
+; GFX9-NEXT: s_and_b32 s2, 0xffff, s2
; GFX9-NEXT: s_lshr_b32 s2, s2, s3
; GFX9-NEXT: s_or_b32 s1, s1, s2
; GFX9-NEXT: s_and_b32 s2, s10, 7
-; GFX9-NEXT: s_and_b32 s3, s7, 0xff
+; GFX9-NEXT: s_bfe_u32 s3, s7, 0x70001
; GFX9-NEXT: s_lshl_b32 s2, s4, s2
-; GFX9-NEXT: s_lshr_b32 s3, s3, 1
; GFX9-NEXT: s_andn2_b32 s4, 7, s10
+; GFX9-NEXT: s_and_b32 s3, 0xffff, s3
; GFX9-NEXT: s_lshr_b32 s3, s3, s4
; GFX9-NEXT: s_or_b32 s2, s2, s3
; GFX9-NEXT: s_and_b32 s3, s11, 7
@@ -1077,38 +999,38 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX10-NEXT: s_lshr_b32 s6, s1, 8
; GFX10-NEXT: s_lshr_b32 s7, s1, 16
; GFX10-NEXT: s_lshr_b32 s8, s1, 24
-; GFX10-NEXT: s_and_b32 s1, s1, 0xff
+; GFX10-NEXT: s_bfe_u32 s1, s1, 0x70001
; GFX10-NEXT: s_lshr_b32 s9, s2, 8
; GFX10-NEXT: s_lshr_b32 s10, s2, 16
; GFX10-NEXT: s_lshr_b32 s11, s2, 24
; GFX10-NEXT: s_and_b32 s12, s2, 7
-; GFX10-NEXT: s_lshr_b32 s1, s1, 1
; GFX10-NEXT: s_andn2_b32 s2, 7, s2
+; GFX10-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX10-NEXT: s_bfe_u32 s6, s6, 0x70001
; GFX10-NEXT: s_lshr_b32 s3, s0, 8
; GFX10-NEXT: s_lshr_b32 s1, s1, s2
-; GFX10-NEXT: s_and_b32 s2, s6, 0xff
-; GFX10-NEXT: s_and_b32 s6, s9, 7
-; GFX10-NEXT: s_lshr_b32 s2, s2, 1
+; GFX10-NEXT: s_and_b32 s2, s9, 7
; GFX10-NEXT: s_andn2_b32 s9, 7, s9
+; GFX10-NEXT: s_and_b32 s6, 0xffff, s6
; GFX10-NEXT: s_lshr_b32 s4, s0, 16
; GFX10-NEXT: s_lshr_b32 s5, s0, 24
; GFX10-NEXT: s_lshl_b32 s0, s0, s12
-; GFX10-NEXT: s_lshl_b32 s3, s3, s6
-; GFX10-NEXT: s_lshr_b32 s2, s2, s9
+; GFX10-NEXT: s_lshl_b32 s2, s3, s2
+; GFX10-NEXT: s_lshr_b32 s3, s6, s9
; GFX10-NEXT: s_or_b32 s0, s0, s1
-; GFX10-NEXT: s_or_b32 s1, s3, s2
-; GFX10-NEXT: s_and_b32 s2, s7, 0xff
-; GFX10-NEXT: s_and_b32 s3, s10, 7
-; GFX10-NEXT: s_lshr_b32 s2, s2, 1
+; GFX10-NEXT: s_or_b32 s1, s2, s3
+; GFX10-NEXT: s_bfe_u32 s3, s7, 0x70001
+; GFX10-NEXT: s_and_b32 s2, s10, 7
; GFX10-NEXT: s_andn2_b32 s6, 7, s10
-; GFX10-NEXT: s_lshl_b32 s3, s4, s3
-; GFX10-NEXT: s_lshr_b32 s2, s2, s6
+; GFX10-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX10-NEXT: s_lshl_b32 s2, s4, s2
+; GFX10-NEXT: s_lshr_b32 s3, s3, s6
; GFX10-NEXT: s_and_b32 s4, s11, 7
; GFX10-NEXT: s_lshr_b32 s6, s8, 1
; GFX10-NEXT: s_andn2_b32 s7, 7, s11
; GFX10-NEXT: s_lshl_b32 s4, s5, s4
; GFX10-NEXT: s_lshr_b32 s5, s6, s7
-; GFX10-NEXT: s_or_b32 s2, s3, s2
+; GFX10-NEXT: s_or_b32 s2, s2, s3
; GFX10-NEXT: s_and_b32 s1, s1, 0xff
; GFX10-NEXT: s_or_b32 s3, s4, s5
; GFX10-NEXT: s_and_b32 s0, s0, 0xff
@@ -1127,38 +1049,38 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX11-NEXT: s_lshr_b32 s6, s1, 8
; GFX11-NEXT: s_lshr_b32 s7, s1, 16
; GFX11-NEXT: s_lshr_b32 s8, s1, 24
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_bfe_u32 s1, s1, 0x70001
; GFX11-NEXT: s_lshr_b32 s9, s2, 8
; GFX11-NEXT: s_lshr_b32 s10, s2, 16
; GFX11-NEXT: s_lshr_b32 s11, s2, 24
; GFX11-NEXT: s_and_b32 s12, s2, 7
-; GFX11-NEXT: s_lshr_b32 s1, s1, 1
; GFX11-NEXT: s_and_not1_b32 s2, 7, s2
+; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX11-NEXT: s_bfe_u32 s6, s6, 0x70001
; GFX11-NEXT: s_lshr_b32 s3, s0, 8
; GFX11-NEXT: s_lshr_b32 s1, s1, s2
-; GFX11-NEXT: s_and_b32 s2, s6, 0xff
-; GFX11-NEXT: s_and_b32 s6, s9, 7
-; GFX11-NEXT: s_lshr_b32 s2, s2, 1
+; GFX11-NEXT: s_and_b32 s2, s9, 7
; GFX11-NEXT: s_and_not1_b32 s9, 7, s9
+; GFX11-NEXT: s_and_b32 s6, 0xffff, s6
; GFX11-NEXT: s_lshr_b32 s4, s0, 16
; GFX11-NEXT: s_lshr_b32 s5, s0, 24
; GFX11-NEXT: s_lshl_b32 s0, s0, s12
-; GFX11-NEXT: s_lshl_b32 s3, s3, s6
-; GFX11-NEXT: s_lshr_b32 s2, s2, s9
+; GFX11-NEXT: s_lshl_b32 s2, s3, s2
+; GFX11-NEXT: s_lshr_b32 s3, s6, s9
; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: s_or_b32 s1, s3, s2
-; GFX11-NEXT: s_and_b32 s2, s7, 0xff
-; GFX11-NEXT: s_and_b32 s3, s10, 7
-; GFX11-NEXT: s_lshr_b32 s2, s2, 1
+; GFX11-NEXT: s_or_b32 s1, s2, s3
+; GFX11-NEXT: s_bfe_u32 s3, s7, 0x70001
+; GFX11-NEXT: s_and_b32 s2, s10, 7
; GFX11-NEXT: s_and_not1_b32 s6, 7, s10
-; GFX11-NEXT: s_lshl_b32 s3, s4, s3
-; GFX11-NEXT: s_lshr_b32 s2, s2, s6
+; GFX11-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX11-NEXT: s_lshl_b32 s2, s4, s2
+; GFX11-NEXT: s_lshr_b32 s3, s3, s6
; GFX11-NEXT: s_and_b32 s4, s11, 7
; GFX11-NEXT: s_lshr_b32 s6, s8, 1
; GFX11-NEXT: s_and_not1_b32 s7, 7, s11
; GFX11-NEXT: s_lshl_b32 s4, s5, s4
; GFX11-NEXT: s_lshr_b32 s5, s6, s7
-; GFX11-NEXT: s_or_b32 s2, s3, s2
+; GFX11-NEXT: s_or_b32 s2, s2, s3
; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_or_b32 s3, s4, s5
; GFX11-NEXT: s_and_b32 s0, s0, 0xff
@@ -1235,46 +1157,45 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX8-LABEL: v_fshl_v4i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v8, 1
-; GFX8-NEXT: v_xor_b32_e32 v10, -1, v2
-; GFX8-NEXT: v_and_b32_e32 v6, 7, v2
-; GFX8-NEXT: v_lshrrev_b16_sdwa v9, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: v_and_b32_e32 v10, 7, v10
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 8, v2
-; GFX8-NEXT: v_lshlrev_b16_e32 v6, v6, v0
-; GFX8-NEXT: v_lshrrev_b16_e32 v9, v10, v9
+; GFX8-NEXT: v_xor_b32_e32 v9, -1, v2
+; GFX8-NEXT: v_and_b32_e32 v7, 7, v2
+; GFX8-NEXT: v_bfe_u32 v8, v1, 1, 7
+; GFX8-NEXT: v_and_b32_e32 v9, 7, v9
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 8, v2
+; GFX8-NEXT: v_lshlrev_b16_e32 v7, v7, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v8, v9, v8
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 8, v1
-; GFX8-NEXT: v_or_b32_e32 v6, v6, v9
-; GFX8-NEXT: v_and_b32_e32 v9, 7, v5
-; GFX8-NEXT: v_xor_b32_e32 v5, -1, v5
+; GFX8-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX8-NEXT: v_and_b32_e32 v8, 7, v6
+; GFX8-NEXT: v_xor_b32_e32 v6, -1, v6
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 8, v0
-; GFX8-NEXT: v_lshrrev_b16_sdwa v4, v8, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: v_and_b32_e32 v5, 7, v5
-; GFX8-NEXT: v_lshlrev_b16_e32 v3, v9, v3
-; GFX8-NEXT: v_lshrrev_b16_e32 v4, v5, v4
-; GFX8-NEXT: v_mov_b32_e32 v7, 0xff
+; GFX8-NEXT: v_bfe_u32 v4, v4, 1, 7
+; GFX8-NEXT: v_and_b32_e32 v6, 7, v6
+; GFX8-NEXT: v_lshlrev_b16_e32 v3, v8, v3
+; GFX8-NEXT: v_lshrrev_b16_e32 v4, v6, v4
; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
; GFX8-NEXT: v_mov_b32_e32 v4, 7
-; GFX8-NEXT: v_mov_b32_e32 v9, -1
-; GFX8-NEXT: v_and_b32_sdwa v5, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_sdwa v7, v1, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_xor_b32_sdwa v10, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_and_b32_sdwa v6, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v8, -1
; GFX8-NEXT: v_and_b32_sdwa v4, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX8-NEXT: v_xor_b32_sdwa v2, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX8-NEXT: v_lshrrev_b16_e32 v7, 1, v7
-; GFX8-NEXT: v_and_b32_e32 v10, 7, v10
-; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; GFX8-NEXT: v_and_b32_e32 v2, 7, v2
-; GFX8-NEXT: v_lshlrev_b16_sdwa v5, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshrrev_b16_e32 v7, v10, v7
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX8-NEXT: v_lshlrev_b16_sdwa v6, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_xor_b32_sdwa v9, v2, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX8-NEXT: v_mov_b32_e32 v4, 1
+; GFX8-NEXT: v_xor_b32_sdwa v2, v2, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX8-NEXT: v_bfe_u32 v5, v5, 1, 7
+; GFX8-NEXT: v_and_b32_e32 v9, 7, v9
+; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX8-NEXT: v_and_b32_e32 v2, 7, v2
+; GFX8-NEXT: v_lshrrev_b16_e32 v5, v9, v5
; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
-; GFX8-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX8-NEXT: v_or_b32_e32 v5, v6, v5
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_mov_b32_e32 v1, 8
; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v5
-; GFX8-NEXT: v_or_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
@@ -1285,47 +1206,47 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX9-LABEL: v_fshl_v4i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v8, 1
-; GFX9-NEXT: v_xor_b32_e32 v10, -1, v2
-; GFX9-NEXT: v_and_b32_e32 v6, 7, v2
-; GFX9-NEXT: v_lshrrev_b16_sdwa v9, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_and_b32_e32 v10, 7, v10
-; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v2
-; GFX9-NEXT: v_lshlrev_b16_e32 v6, v6, v0
-; GFX9-NEXT: v_lshrrev_b16_e32 v9, v10, v9
+; GFX9-NEXT: v_xor_b32_e32 v9, -1, v2
+; GFX9-NEXT: v_and_b32_e32 v7, 7, v2
+; GFX9-NEXT: v_bfe_u32 v8, v1, 1, 7
+; GFX9-NEXT: v_and_b32_e32 v9, 7, v9
+; GFX9-NEXT: v_lshrrev_b32_e32 v6, 8, v2
+; GFX9-NEXT: v_lshlrev_b16_e32 v7, v7, v0
+; GFX9-NEXT: v_lshrrev_b16_e32 v8, v9, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 8, v1
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v9
-; GFX9-NEXT: v_and_b32_e32 v9, 7, v5
-; GFX9-NEXT: v_xor_b32_e32 v5, -1, v5
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_and_b32_e32 v8, 7, v6
+; GFX9-NEXT: v_xor_b32_e32 v6, -1, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v0
-; GFX9-NEXT: v_lshrrev_b16_sdwa v4, v8, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: v_and_b32_e32 v5, 7, v5
-; GFX9-NEXT: v_lshlrev_b16_e32 v3, v9, v3
-; GFX9-NEXT: v_lshrrev_b16_e32 v4, v5, v4
-; GFX9-NEXT: v_mov_b32_e32 v7, 0xff
+; GFX9-NEXT: v_bfe_u32 v4, v4, 1, 7
+; GFX9-NEXT: v_and_b32_e32 v6, 7, v6
+; GFX9-NEXT: v_lshlrev_b16_e32 v3, v8, v3
+; GFX9-NEXT: v_lshrrev_b16_e32 v4, v6, v4
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: v_mov_b32_e32 v4, 7
-; GFX9-NEXT: v_mov_b32_e32 v10, -1
-; GFX9-NEXT: v_and_b32_sdwa v5, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-NEXT: v_and_b32_sdwa v9, v1, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9-NEXT: v_xor_b32_sdwa v11, v2, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_sdwa v6, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-NEXT: v_mov_b32_e32 v8, -1
; GFX9-NEXT: v_and_b32_sdwa v4, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX9-NEXT: v_xor_b32_sdwa v2, v2, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX9-NEXT: v_lshrrev_b16_e32 v9, 1, v9
-; GFX9-NEXT: v_and_b32_e32 v11, 7, v11
-; GFX9-NEXT: v_lshrrev_b16_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; GFX9-NEXT: v_and_b32_e32 v2, 7, v2
-; GFX9-NEXT: v_lshlrev_b16_sdwa v5, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-NEXT: v_lshrrev_b16_e32 v9, v11, v9
+; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX9-NEXT: v_lshlrev_b16_sdwa v6, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_xor_b32_sdwa v9, v2, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX9-NEXT: v_mov_b32_e32 v4, 1
+; GFX9-NEXT: v_xor_b32_sdwa v2, v2, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX9-NEXT: v_bfe_u32 v5, v5, 1, 7
+; GFX9-NEXT: v_and_b32_e32 v9, 7, v9
+; GFX9-NEXT: v_lshrrev_b16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX9-NEXT: v_and_b32_e32 v2, 7, v2
+; GFX9-NEXT: v_lshrrev_b16_e32 v5, v9, v5
; GFX9-NEXT: v_lshrrev_b16_e32 v1, v2, v1
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v9
+; GFX9-NEXT: v_mov_b32_e32 v2, 8
+; GFX9-NEXT: v_or_b32_e32 v5, v6, v5
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_mov_b32_e32 v1, 8
-; GFX9-NEXT: v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xff
+; GFX9-NEXT: v_lshlrev_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_and_or_b32 v1, v7, v1, v2
; GFX9-NEXT: v_and_b32_e32 v2, 0xff, v5
; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX9-NEXT: v_and_or_b32 v1, v6, v7, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX9-NEXT: v_or3_b32 v0, v1, v2, v0
@@ -1334,52 +1255,49 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX10-LABEL: v_fshl_v4i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshrrev_b32_e32 v6, 8, v2
+; GFX10-NEXT: v_and_b32_e32 v7, 7, v2
+; GFX10-NEXT: v_lshrrev_b32_e32 v9, 8, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 8, v0
-; GFX10-NEXT: v_and_b32_e32 v8, 7, v2
-; GFX10-NEXT: v_and_b32_e32 v9, 0xff, v1
-; GFX10-NEXT: v_xor_b32_e32 v10, -1, v2
-; GFX10-NEXT: v_and_b32_e32 v11, 7, v6
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 24, v0
-; GFX10-NEXT: v_lshrrev_b32_e32 v7, 8, v1
-; GFX10-NEXT: v_lshlrev_b16 v0, v8, v0
-; GFX10-NEXT: v_lshrrev_b16 v8, 1, v9
-; GFX10-NEXT: v_and_b32_e32 v9, 7, v10
-; GFX10-NEXT: v_lshlrev_b16 v3, v11, v3
-; GFX10-NEXT: v_mov_b32_e32 v10, 0xff
-; GFX10-NEXT: v_mov_b32_e32 v11, -1
-; GFX10-NEXT: v_lshrrev_b32_e32 v12, 24, v1
-; GFX10-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX10-NEXT: v_xor_b32_e32 v6, -1, v6
+; GFX10-NEXT: v_lshlrev_b16 v0, v7, v0
+; GFX10-NEXT: v_and_b32_e32 v7, 7, v9
+; GFX10-NEXT: v_mov_b32_e32 v12, -1
+; GFX10-NEXT: v_lshrrev_b32_e32 v6, 8, v1
+; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX10-NEXT: v_lshrrev_b32_e32 v11, 24, v1
+; GFX10-NEXT: v_xor_b32_e32 v9, -1, v9
; GFX10-NEXT: v_mov_b32_e32 v13, 7
-; GFX10-NEXT: v_and_b32_sdwa v1, v1, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX10-NEXT: v_xor_b32_sdwa v10, v2, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX10-NEXT: v_xor_b32_sdwa v11, v2, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX10-NEXT: v_lshrrev_b16 v7, 1, v7
-; GFX10-NEXT: v_and_b32_e32 v6, 7, v6
+; GFX10-NEXT: v_lshlrev_b16 v3, v7, v3
+; GFX10-NEXT: v_xor_b32_sdwa v7, v2, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-NEXT: v_xor_b32_sdwa v12, v2, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX10-NEXT: v_xor_b32_e32 v10, -1, v2
+; GFX10-NEXT: v_bfe_u32 v6, v6, 1, 7
+; GFX10-NEXT: v_and_b32_e32 v9, 7, v9
; GFX10-NEXT: v_and_b32_sdwa v14, v2, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX10-NEXT: v_lshrrev_b16 v1, 1, v1
-; GFX10-NEXT: v_and_b32_e32 v10, 7, v10
+; GFX10-NEXT: v_bfe_u32 v8, v8, 1, 7
+; GFX10-NEXT: v_and_b32_e32 v7, 7, v7
; GFX10-NEXT: v_and_b32_sdwa v2, v2, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX10-NEXT: v_lshrrev_b16 v12, 1, v12
-; GFX10-NEXT: v_and_b32_e32 v11, 7, v11
-; GFX10-NEXT: v_lshrrev_b16 v6, v6, v7
+; GFX10-NEXT: v_lshrrev_b16 v11, 1, v11
+; GFX10-NEXT: v_and_b32_e32 v12, 7, v12
+; GFX10-NEXT: v_bfe_u32 v1, v1, 1, 7
+; GFX10-NEXT: v_and_b32_e32 v10, 7, v10
+; GFX10-NEXT: v_lshrrev_b16 v6, v9, v6
; GFX10-NEXT: v_lshlrev_b16 v4, v14, v4
-; GFX10-NEXT: v_lshrrev_b16 v1, v10, v1
+; GFX10-NEXT: v_lshrrev_b16 v7, v7, v8
; GFX10-NEXT: v_lshlrev_b16 v2, v2, v5
-; GFX10-NEXT: v_lshrrev_b16 v5, v11, v12
-; GFX10-NEXT: v_lshrrev_b16 v7, v9, v8
+; GFX10-NEXT: v_lshrrev_b16 v5, v12, v11
+; GFX10-NEXT: v_lshrrev_b16 v1, v10, v1
; GFX10-NEXT: v_or_b32_e32 v3, v3, v6
; GFX10-NEXT: v_mov_b32_e32 v6, 8
-; GFX10-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX10-NEXT: v_or_b32_e32 v4, v4, v7
; GFX10-NEXT: v_or_b32_e32 v2, v2, v5
-; GFX10-NEXT: v_or_b32_e32 v0, v0, v7
-; GFX10-NEXT: v_lshlrev_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX10-NEXT: v_lshlrev_b32_sdwa v1, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v4
; GFX10-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX10-NEXT: v_and_or_b32 v0, 0xff, v0, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX10-NEXT: v_and_or_b32 v0, 0xff, v0, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -1387,42 +1305,39 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX11-LABEL: v_fshl_v4i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshrrev_b32_e32 v7, 8, v2
; GFX11-NEXT: v_lshrrev_b32_e32 v6, 8, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v9, 8, v2
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v0
-; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v6
-; GFX11-NEXT: v_xor_b32_e32 v13, -1, v9
; GFX11-NEXT: v_lshrrev_b32_e32 v11, 24, v2
-; GFX11-NEXT: v_and_b32_e32 v9, 7, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v8, 24, v1
-; GFX11-NEXT: v_lshrrev_b16 v6, 1, v6
-; GFX11-NEXT: v_and_b32_e32 v13, 7, v13
-; GFX11-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-NEXT: v_lshlrev_b16 v3, v9, v3
-; GFX11-NEXT: v_xor_b32_e32 v9, -1, v10
+; GFX11-NEXT: v_xor_b32_e32 v12, -1, v7
+; GFX11-NEXT: v_and_b32_e32 v7, 7, v7
+; GFX11-NEXT: v_bfe_u32 v6, v6, 1, 7
+; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v9, 24, v1
+; GFX11-NEXT: v_and_b32_e32 v12, 7, v12
+; GFX11-NEXT: v_lshlrev_b16 v3, v7, v3
+; GFX11-NEXT: v_xor_b32_e32 v7, -1, v10
; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-NEXT: v_lshrrev_b16 v6, v13, v6
-; GFX11-NEXT: v_xor_b32_e32 v13, -1, v11
; GFX11-NEXT: v_lshrrev_b32_e32 v5, 24, v0
-; GFX11-NEXT: v_and_b32_e32 v12, 7, v2
-; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT: v_lshrrev_b16 v6, v12, v6
+; GFX11-NEXT: v_xor_b32_e32 v12, -1, v11
+; GFX11-NEXT: v_and_b32_e32 v13, 7, v2
; GFX11-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX11-NEXT: v_and_b32_e32 v10, 7, v10
-; GFX11-NEXT: v_lshrrev_b16 v7, 1, v7
-; GFX11-NEXT: v_and_b32_e32 v9, 7, v9
+; GFX11-NEXT: v_bfe_u32 v8, v8, 1, 7
+; GFX11-NEXT: v_and_b32_e32 v7, 7, v7
; GFX11-NEXT: v_and_b32_e32 v11, 7, v11
-; GFX11-NEXT: v_lshrrev_b16 v8, 1, v8
-; GFX11-NEXT: v_and_b32_e32 v13, 7, v13
-; GFX11-NEXT: v_lshrrev_b16 v1, 1, v1
+; GFX11-NEXT: v_lshrrev_b16 v9, 1, v9
+; GFX11-NEXT: v_and_b32_e32 v12, 7, v12
+; GFX11-NEXT: v_bfe_u32 v1, v1, 1, 7
; GFX11-NEXT: v_and_b32_e32 v2, 7, v2
; GFX11-NEXT: v_or_b32_e32 v3, v3, v6
; GFX11-NEXT: v_lshlrev_b16 v4, v10, v4
-; GFX11-NEXT: v_lshrrev_b16 v6, v9, v7
+; GFX11-NEXT: v_lshrrev_b16 v6, v7, v8
; GFX11-NEXT: v_lshlrev_b16 v5, v11, v5
-; GFX11-NEXT: v_lshrrev_b16 v7, v13, v8
-; GFX11-NEXT: v_lshlrev_b16 v0, v12, v0
+; GFX11-NEXT: v_lshrrev_b16 v7, v12, v9
+; GFX11-NEXT: v_lshlrev_b16 v0, v13, v0
; GFX11-NEXT: v_lshrrev_b16 v1, v2, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v3
; GFX11-NEXT: v_or_b32_e32 v3, v4, v6
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index 2e8c918e4c67e..5886b5d98f771 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -463,42 +463,17 @@ define i8 @v_fshr_i8(i8 %lhs, i8 %rhs, i8 %amt) {
}
define amdgpu_ps i8 @s_fshr_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
-; GFX6-LABEL: s_fshr_i8_4:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshl_b32 s0, s0, 4
-; GFX6-NEXT: s_bfe_u32 s1, s1, 0x40004
-; GFX6-NEXT: s_or_b32 s0, s0, s1
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshr_i8_4:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_and_b32 s1, s1, 0xff
-; GFX8-NEXT: s_lshl_b32 s0, s0, 4
-; GFX8-NEXT: s_lshr_b32 s1, s1, 4
-; GFX8-NEXT: s_or_b32 s0, s0, s1
-; GFX8-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: s_fshr_i8_4:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_and_b32 s1, s1, 0xff
-; GFX9-NEXT: s_lshl_b32 s0, s0, 4
-; GFX9-NEXT: s_lshr_b32 s1, s1, 4
-; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: ; return to shader part epilog
-;
-; GFX10-LABEL: s_fshr_i8_4:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_and_b32 s1, s1, 0xff
-; GFX10-NEXT: s_lshl_b32 s0, s0, 4
-; GFX10-NEXT: s_lshr_b32 s1, s1, 4
-; GFX10-NEXT: s_or_b32 s0, s0, s1
-; GFX10-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshr_i8_4:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_lshl_b32 s0, s0, 4
+; GCN-NEXT: s_bfe_u32 s1, s1, 0x40004
+; GCN-NEXT: s_or_b32 s0, s0, s1
+; GCN-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_fshr_i8_4:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_lshl_b32 s0, s0, 4
-; GFX11-NEXT: s_lshr_b32 s1, s1, 4
+; GFX11-NEXT: s_bfe_u32 s1, s1, 0x40004
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_or_b32 s0, s0, s1
; GFX11-NEXT: ; return to shader part epilog
@@ -518,37 +493,33 @@ define i8 @v_fshr_i8_4(i8 %lhs, i8 %rhs) {
; GFX8-LABEL: v_fshr_i8_4:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v2, 4
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 4, v0
-; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_bfe_u32 v1, v1, 4, 4
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshr_i8_4:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v2, 4
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 4, v0
-; GFX9-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_bfe_u32 v1, v1, 4, 4
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fshr_i8_4:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-NEXT: v_lshlrev_b16 v0, 4, v0
-; GFX10-NEXT: v_lshrrev_b16 v1, 4, v1
+; GFX10-NEXT: v_bfe_u32 v1, v1, 4, 4
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fshr_i8_4:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_lshlrev_b16 v0, 4, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b16 v1, 4, v1
+; GFX11-NEXT: v_bfe_u32 v1, v1, 4, 4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 4)
@@ -556,42 +527,17 @@ define i8 @v_fshr_i8_4(i8 %lhs, i8 %rhs) {
}
define amdgpu_ps i8 @s_fshr_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
-; GFX6-LABEL: s_fshr_i8_5:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_lshl_b32 s0, s0, 3
-; GFX6-NEXT: s_bfe_u32 s1, s1, 0x30005
-; GFX6-NEXT: s_or_b32 s0, s0, s1
-; GFX6-NEXT: ; return to shader part epilog
-;
-; GFX8-LABEL: s_fshr_i8_5:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_and_b32 s1, s1, 0xff
-; GFX8-NEXT: s_lshl_b32 s0, s0, 3
-; GFX8-NEXT: s_lshr_b32 s1, s1, 5
-; GFX8-NEXT: s_or_b32 s0, s0, s1
-; GFX8-NEXT: ; return to shader part epilog
-;
-; GFX9-LABEL: s_fshr_i8_5:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_and_b32 s1, s1, 0xff
-; GFX9-NEXT: s_lshl_b32 s0, s0, 3
-; GFX9-NEXT: s_lshr_b32 s1, s1, 5
-; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: ; return to shader part epilog
-;
-; GFX10-LABEL: s_fshr_i8_5:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_and_b32 s1, s1, 0xff
-; GFX10-NEXT: s_lshl_b32 s0, s0, 3
-; GFX10-NEXT: s_lshr_b32 s1, s1, 5
-; GFX10-NEXT: s_or_b32 s0, s0, s1
-; GFX10-NEXT: ; return to shader part epilog
+; GCN-LABEL: s_fshr_i8_5:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_lshl_b32 s0, s0, 3
+; GCN-NEXT: s_bfe_u32 s1, s1, 0x30005
+; GCN-NEXT: s_or_b32 s0, s0, s1
+; GCN-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_fshr_i8_5:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_lshl_b32 s0, s0, 3
-; GFX11-NEXT: s_lshr_b32 s1, s1, 5
+; GFX11-NEXT: s_bfe_u32 s1, s1, 0x30005
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_or_b32 s0, s0, s1
; GFX11-NEXT: ; return to shader part epilog
@@ -611,37 +557,33 @@ define i8 @v_fshr_i8_5(i8 %lhs, i8 %rhs) {
; GFX8-LABEL: v_fshr_i8_5:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v2, 5
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 3, v0
-; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_bfe_u32 v1, v1, 5, 3
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshr_i8_5:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v2, 5
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 3, v0
-; GFX9-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_bfe_u32 v1, v1, 5, 3
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fshr_i8_5:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-NEXT: v_lshlrev_b16 v0, 3, v0
-; GFX10-NEXT: v_lshrrev_b16 v1, 5, v1
+; GFX10-NEXT: v_bfe_u32 v1, v1, 5, 3
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fshr_i8_5:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_lshlrev_b16 v0, 3, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b16 v1, 5, v1
+; GFX11-NEXT: v_bfe_u32 v1, v1, 5, 3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 5)
@@ -3455,26 +3397,24 @@ define amdgpu_ps i32 @s_fshr_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, <
; GFX8-NEXT: s_lshr_b32 s4, s1, 16
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
; GFX8-NEXT: s_lshr_b32 s5, s5, 15
-; GFX8-NEXT: s_lshl_b32 s1, s1, 1
; GFX8-NEXT: s_or_b32 s0, s0, s5
; GFX8-NEXT: s_lshl_b32 s3, s3, 1
; GFX8-NEXT: s_lshr_b32 s5, s4, 15
; GFX8-NEXT: s_xor_b32 s2, s2, -1
-; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX8-NEXT: s_bfe_u32 s1, s1, 0xf0000
; GFX8-NEXT: s_or_b32 s3, s3, s5
; GFX8-NEXT: s_lshr_b32 s5, s2, 16
; GFX8-NEXT: s_and_b32 s6, s2, 15
; GFX8-NEXT: s_andn2_b32 s2, 15, s2
-; GFX8-NEXT: s_lshr_b32 s1, s1, 1
+; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_lshl_b32 s0, s0, s6
; GFX8-NEXT: s_lshr_b32 s1, s1, s2
-; GFX8-NEXT: s_lshl_b32 s4, s4, 1
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: s_and_b32 s1, s5, 15
; GFX8-NEXT: s_lshl_b32 s1, s3, s1
-; GFX8-NEXT: s_and_b32 s3, 0xffff, s4
+; GFX8-NEXT: s_bfe_u32 s3, s4, 0xf0000
; GFX8-NEXT: s_andn2_b32 s2, 15, s5
-; GFX8-NEXT: s_lshr_b32 s3, s3, 1
+; GFX8-NEXT: s_and_b32 s3, 0xffff, s3
; GFX8-NEXT: s_lshr_b32 s2, s3, s2
; GFX8-NEXT: s_or_b32 s1, s1, s2
; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
@@ -3596,35 +3536,34 @@ define <2 x i16> @v_fshr_v2i16(<2 x i16> %lhs, <2 x i16> %rhs, <2 x i16> %amt) {
; GFX8-LABEL: v_fshr_v2i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b16_e32 v3, 1, v0
-; GFX8-NEXT: v_lshrrev_b16_e32 v4, 15, v1
-; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX8-NEXT: v_mov_b32_e32 v4, 1
+; GFX8-NEXT: v_lshlrev_b16_e32 v4, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v5, 15, v1
+; GFX8-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX8-NEXT: v_mov_b32_e32 v5, 1
+; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_mov_b32_e32 v5, 15
-; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshrrev_b16_sdwa v6, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_xor_b32_e32 v2, -1, v2
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v6
-; GFX8-NEXT: v_lshlrev_b16_e32 v6, 1, v1
-; GFX8-NEXT: v_lshlrev_b16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_and_b32_e32 v4, 15, v2
+; GFX8-NEXT: v_lshrrev_b16_sdwa v6, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_xor_b32_e32 v7, -1, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v6
+; GFX8-NEXT: v_and_b32_e32 v6, 15, v2
; GFX8-NEXT: v_and_b32_e32 v7, 15, v7
-; GFX8-NEXT: v_lshlrev_b16_e32 v3, v4, v3
-; GFX8-NEXT: v_lshrrev_b16_e32 v4, 1, v6
-; GFX8-NEXT: v_lshrrev_b16_e32 v4, v7, v4
-; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX8-NEXT: v_bfe_u32 v1, v1, 0, 15
+; GFX8-NEXT: v_lshlrev_b16_e32 v4, v6, v4
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, v7, v1
+; GFX8-NEXT: v_or_b32_e32 v1, v4, v1
; GFX8-NEXT: v_and_b32_sdwa v4, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_mov_b32_e32 v5, -1
; GFX8-NEXT: v_xor_b32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_e32 v2, 15, v2
-; GFX8-NEXT: v_lshrrev_b16_e32 v1, 1, v1
+; GFX8-NEXT: v_bfe_u32 v3, v3, 0, 15
; GFX8-NEXT: v_lshlrev_b16_e32 v0, v4, v0
-; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, v2, v3
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshr_v2i16:
@@ -3777,28 +3716,24 @@ define amdgpu_ps float @v_fshr_v2i16_ssv(<2 x i16> inreg %lhs, <2 x i16> inreg %
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
; GFX8-NEXT: s_lshr_b32 s4, s4, 15
; GFX8-NEXT: v_xor_b32_e32 v0, -1, v0
-; GFX8-NEXT: s_lshr_b32 s3, s1, 16
; GFX8-NEXT: s_or_b32 s0, s0, s4
-; GFX8-NEXT: s_lshl_b32 s1, s1, 1
; GFX8-NEXT: v_and_b32_e32 v1, 15, v0
; GFX8-NEXT: v_xor_b32_e32 v2, -1, v0
-; GFX8-NEXT: v_lshlrev_b16_e64 v1, v1, s0
-; GFX8-NEXT: s_and_b32 s0, 0xffff, s1
; GFX8-NEXT: v_and_b32_e32 v2, 15, v2
-; GFX8-NEXT: s_lshr_b32 s0, s0, 1
+; GFX8-NEXT: v_lshlrev_b16_e64 v1, v1, s0
+; GFX8-NEXT: s_bfe_u32 s0, s1, 0xf0000
; GFX8-NEXT: v_lshrrev_b16_e64 v2, v2, s0
-; GFX8-NEXT: s_lshr_b32 s4, s3, 15
-; GFX8-NEXT: s_lshl_b32 s3, s3, 1
+; GFX8-NEXT: s_lshr_b32 s3, s1, 16
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: v_mov_b32_e32 v2, 15
; GFX8-NEXT: v_mov_b32_e32 v3, -1
; GFX8-NEXT: s_lshl_b32 s2, s2, 1
+; GFX8-NEXT: s_lshr_b32 s4, s3, 15
; GFX8-NEXT: v_and_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_xor_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: s_and_b32 s0, 0xffff, s3
; GFX8-NEXT: s_or_b32 s2, s2, s4
; GFX8-NEXT: v_and_b32_e32 v0, 15, v0
-; GFX8-NEXT: s_lshr_b32 s0, s0, 1
+; GFX8-NEXT: s_bfe_u32 s0, s3, 0xf0000
; GFX8-NEXT: v_lshlrev_b16_e64 v2, v2, s2
; GFX8-NEXT: v_lshrrev_b16_e64 v0, v0, s0
; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
@@ -3894,32 +3829,30 @@ define amdgpu_ps float @v_fshr_v2i16_svs(<2 x i16> inreg %lhs, <2 x i16> %rhs, <
; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s2, s0, 16
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
-; GFX8-NEXT: v_lshrrev_b16_e32 v1, 15, v0
-; GFX8-NEXT: v_mov_b32_e32 v2, 15
-; GFX8-NEXT: v_or_b32_e32 v1, s0, v1
-; GFX8-NEXT: s_lshl_b32 s0, s2, 1
-; GFX8-NEXT: v_lshrrev_b16_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 15, v0
+; GFX8-NEXT: v_mov_b32_e32 v3, 15
; GFX8-NEXT: v_or_b32_e32 v2, s0, v2
-; GFX8-NEXT: v_lshlrev_b16_e32 v3, 1, v0
-; GFX8-NEXT: v_mov_b32_e32 v4, 1
+; GFX8-NEXT: s_lshl_b32 s0, s2, 1
+; GFX8-NEXT: v_lshrrev_b16_sdwa v3, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_or_b32_e32 v3, s0, v3
; GFX8-NEXT: s_xor_b32 s0, s1, -1
-; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX8-NEXT: s_lshr_b32 s1, s0, 16
; GFX8-NEXT: s_and_b32 s2, s0, 15
; GFX8-NEXT: s_andn2_b32 s0, 15, s0
-; GFX8-NEXT: v_lshrrev_b16_e32 v3, 1, v3
-; GFX8-NEXT: v_lshrrev_b16_e32 v3, s0, v3
+; GFX8-NEXT: v_bfe_u32 v0, v0, 0, 15
+; GFX8-NEXT: v_lshlrev_b16_e32 v2, s2, v2
+; GFX8-NEXT: v_lshrrev_b16_e32 v0, s0, v0
; GFX8-NEXT: s_and_b32 s0, s1, 15
; GFX8-NEXT: s_andn2_b32 s1, 15, s1
-; GFX8-NEXT: v_lshrrev_b16_e32 v0, 1, v0
-; GFX8-NEXT: v_lshlrev_b16_e32 v2, s0, v2
-; GFX8-NEXT: v_lshrrev_b16_e32 v0, s1, v0
+; GFX8-NEXT: v_bfe_u32 v1, v1, 0, 15
; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX8-NEXT: v_lshlrev_b16_e32 v1, s2, v1
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b16_e32 v2, s0, v3
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, s1, v1
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: v_fshr_v2i16_svs:
@@ -4022,26 +3955,24 @@ define amdgpu_ps float @v_fshr_v2i16_vss(<2 x i16> %lhs, <2 x i16> inreg %rhs, <
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 1, v0
; GFX8-NEXT: s_lshr_b32 s3, s3, 15
; GFX8-NEXT: v_mov_b32_e32 v2, 1
-; GFX8-NEXT: s_lshl_b32 s0, s0, 1
; GFX8-NEXT: v_or_b32_e32 v1, s3, v1
; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: s_lshr_b32 s3, s2, 15
; GFX8-NEXT: s_xor_b32 s1, s1, -1
-; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX8-NEXT: s_bfe_u32 s0, s0, 0xf0000
; GFX8-NEXT: v_or_b32_e32 v0, s3, v0
; GFX8-NEXT: s_lshr_b32 s3, s1, 16
; GFX8-NEXT: s_and_b32 s4, s1, 15
; GFX8-NEXT: s_andn2_b32 s1, 15, s1
-; GFX8-NEXT: s_lshr_b32 s0, s0, 1
+; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
; GFX8-NEXT: v_lshlrev_b16_e32 v1, s4, v1
; GFX8-NEXT: s_lshr_b32 s0, s0, s1
-; GFX8-NEXT: s_lshl_b32 s2, s2, 1
; GFX8-NEXT: v_or_b32_e32 v1, s0, v1
; GFX8-NEXT: s_and_b32 s0, s3, 15
; GFX8-NEXT: v_lshlrev_b16_e32 v0, s0, v0
-; GFX8-NEXT: s_and_b32 s0, 0xffff, s2
+; GFX8-NEXT: s_bfe_u32 s0, s2, 0xf0000
; GFX8-NEXT: s_andn2_b32 s1, 15, s3
-; GFX8-NEXT: s_lshr_b32 s0, s0, 1
+; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
; GFX8-NEXT: s_lshr_b32 s0, s0, s1
; GFX8-NEXT: v_or_b32_e32 v0, s0, v0
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -4158,38 +4089,35 @@ define amdgpu_ps i48 @s_fshr_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs, <
; GFX8-NEXT: s_lshr_b32 s7, s2, 16
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
; GFX8-NEXT: s_lshr_b32 s8, s8, 15
-; GFX8-NEXT: s_lshl_b32 s2, s2, 1
; GFX8-NEXT: s_or_b32 s0, s0, s8
; GFX8-NEXT: s_lshl_b32 s6, s6, 1
; GFX8-NEXT: s_lshr_b32 s8, s7, 15
; GFX8-NEXT: s_xor_b32 s4, s4, -1
-; GFX8-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX8-NEXT: s_bfe_u32 s2, s2, 0xf0000
; GFX8-NEXT: s_or_b32 s6, s6, s8
; GFX8-NEXT: s_lshr_b32 s8, s4, 16
; GFX8-NEXT: s_and_b32 s9, s4, 15
; GFX8-NEXT: s_andn2_b32 s4, 15, s4
-; GFX8-NEXT: s_lshr_b32 s2, s2, 1
+; GFX8-NEXT: s_and_b32 s2, 0xffff, s2
; GFX8-NEXT: s_lshl_b32 s0, s0, s9
; GFX8-NEXT: s_lshr_b32 s2, s2, s4
-; GFX8-NEXT: s_lshl_b32 s7, s7, 1
; GFX8-NEXT: s_or_b32 s0, s0, s2
; GFX8-NEXT: s_and_b32 s2, s8, 15
; GFX8-NEXT: s_lshl_b32 s2, s6, s2
-; GFX8-NEXT: s_and_b32 s6, 0xffff, s7
+; GFX8-NEXT: s_bfe_u32 s6, s7, 0xf0000
; GFX8-NEXT: s_andn2_b32 s4, 15, s8
-; GFX8-NEXT: s_lshr_b32 s6, s6, 1
+; GFX8-NEXT: s_and_b32 s6, 0xffff, s6
; GFX8-NEXT: s_lshr_b32 s4, s6, s4
; GFX8-NEXT: s_or_b32 s2, s2, s4
; GFX8-NEXT: s_and_b32 s4, 0xffff, s3
; GFX8-NEXT: s_lshl_b32 s1, s1, 1
; GFX8-NEXT: s_lshr_b32 s4, s4, 15
-; GFX8-NEXT: s_lshl_b32 s3, s3, 1
; GFX8-NEXT: s_or_b32 s1, s1, s4
; GFX8-NEXT: s_xor_b32 s4, s5, -1
-; GFX8-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX8-NEXT: s_bfe_u32 s3, s3, 0xf0000
; GFX8-NEXT: s_and_b32 s5, s4, 15
; GFX8-NEXT: s_andn2_b32 s4, 15, s4
-; GFX8-NEXT: s_lshr_b32 s3, s3, 1
+; GFX8-NEXT: s_and_b32 s3, 0xffff, s3
; GFX8-NEXT: s_lshl_b32 s1, s1, s5
; GFX8-NEXT: s_lshr_b32 s3, s3, s4
; GFX8-NEXT: s_and_b32 s2, 0xffff, s2
@@ -4399,47 +4327,45 @@ define <3 x half> @v_fshr_v3i16(<3 x i16> %lhs, <3 x i16> %rhs, <3 x i16> %amt)
; GFX8-LABEL: v_fshr_v3i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b16_e32 v6, 1, v0
-; GFX8-NEXT: v_lshrrev_b16_e32 v7, 15, v2
-; GFX8-NEXT: v_or_b32_e32 v6, v6, v7
-; GFX8-NEXT: v_mov_b32_e32 v7, 1
-; GFX8-NEXT: v_mov_b32_e32 v8, 15
-; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshrrev_b16_sdwa v9, v8, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_lshlrev_b16_e32 v7, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v8, 15, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; GFX8-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX8-NEXT: v_mov_b32_e32 v8, 1
; GFX8-NEXT: v_xor_b32_e32 v4, -1, v4
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v9
-; GFX8-NEXT: v_lshlrev_b16_e32 v9, 1, v2
-; GFX8-NEXT: v_lshlrev_b16_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_and_b32_e32 v7, 15, v4
-; GFX8-NEXT: v_xor_b32_e32 v10, -1, v4
-; GFX8-NEXT: v_and_b32_e32 v10, 15, v10
-; GFX8-NEXT: v_lshlrev_b16_e32 v6, v7, v6
-; GFX8-NEXT: v_lshrrev_b16_e32 v7, 1, v9
-; GFX8-NEXT: v_lshrrev_b16_e32 v7, v10, v7
-; GFX8-NEXT: v_or_b32_e32 v6, v6, v7
-; GFX8-NEXT: v_and_b32_sdwa v7, v4, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_lshrrev_b16_e32 v8, 15, v6
+; GFX8-NEXT: v_xor_b32_e32 v9, -1, v4
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v8
+; GFX8-NEXT: v_and_b32_e32 v8, 15, v4
+; GFX8-NEXT: v_and_b32_e32 v9, 15, v9
+; GFX8-NEXT: v_bfe_u32 v2, v2, 0, 15
+; GFX8-NEXT: v_lshlrev_b16_e32 v7, v8, v7
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, v9, v2
+; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX8-NEXT: v_mov_b32_e32 v7, 15
; GFX8-NEXT: v_mov_b32_e32 v8, -1
+; GFX8-NEXT: v_and_b32_sdwa v7, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_xor_b32_sdwa v4, v4, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_e32 v4, 15, v4
-; GFX8-NEXT: v_lshrrev_b16_e32 v2, 1, v2
+; GFX8-NEXT: v_bfe_u32 v6, v6, 0, 15
; GFX8-NEXT: v_lshlrev_b16_e32 v0, v7, v0
-; GFX8-NEXT: v_lshrrev_b16_e32 v2, v4, v2
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-NEXT: v_lshrrev_b16_e32 v4, v4, v6
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 1, v1
-; GFX8-NEXT: v_lshrrev_b16_e32 v2, 15, v3
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX8-NEXT: v_lshlrev_b16_e32 v2, 1, v3
-; GFX8-NEXT: v_xor_b32_e32 v3, -1, v5
-; GFX8-NEXT: v_and_b32_e32 v4, 15, v3
-; GFX8-NEXT: v_xor_b32_e32 v3, -1, v3
-; GFX8-NEXT: v_and_b32_e32 v3, 15, v3
-; GFX8-NEXT: v_lshrrev_b16_e32 v2, 1, v2
-; GFX8-NEXT: v_lshlrev_b16_e32 v1, v4, v1
-; GFX8-NEXT: v_lshrrev_b16_e32 v2, v3, v2
+; GFX8-NEXT: v_lshrrev_b16_e32 v4, 15, v3
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
+; GFX8-NEXT: v_xor_b32_e32 v4, -1, v5
+; GFX8-NEXT: v_and_b32_e32 v5, 15, v4
+; GFX8-NEXT: v_xor_b32_e32 v4, -1, v4
+; GFX8-NEXT: v_and_b32_e32 v4, 15, v4
+; GFX8-NEXT: v_bfe_u32 v3, v3, 0, 15
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, v5, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, v4, v3
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_or_b32_sdwa v0, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -4580,26 +4506,24 @@ define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %
; GFX8-NEXT: s_lshr_b32 s7, s2, 16
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
; GFX8-NEXT: s_lshr_b32 s8, s8, 15
-; GFX8-NEXT: s_lshl_b32 s2, s2, 1
; GFX8-NEXT: s_or_b32 s0, s0, s8
; GFX8-NEXT: s_lshl_b32 s6, s6, 1
; GFX8-NEXT: s_lshr_b32 s8, s7, 15
; GFX8-NEXT: s_xor_b32 s4, s4, -1
-; GFX8-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX8-NEXT: s_bfe_u32 s2, s2, 0xf0000
; GFX8-NEXT: s_or_b32 s6, s6, s8
; GFX8-NEXT: s_lshr_b32 s8, s4, 16
; GFX8-NEXT: s_and_b32 s9, s4, 15
; GFX8-NEXT: s_andn2_b32 s4, 15, s4
-; GFX8-NEXT: s_lshr_b32 s2, s2, 1
+; GFX8-NEXT: s_and_b32 s2, 0xffff, s2
; GFX8-NEXT: s_lshl_b32 s0, s0, s9
; GFX8-NEXT: s_lshr_b32 s2, s2, s4
-; GFX8-NEXT: s_lshl_b32 s7, s7, 1
; GFX8-NEXT: s_or_b32 s0, s0, s2
; GFX8-NEXT: s_and_b32 s2, s8, 15
; GFX8-NEXT: s_lshl_b32 s2, s6, s2
-; GFX8-NEXT: s_and_b32 s6, 0xffff, s7
+; GFX8-NEXT: s_bfe_u32 s6, s7, 0xf0000
; GFX8-NEXT: s_andn2_b32 s4, 15, s8
-; GFX8-NEXT: s_lshr_b32 s6, s6, 1
+; GFX8-NEXT: s_and_b32 s6, 0xffff, s6
; GFX8-NEXT: s_lshr_b32 s4, s6, s4
; GFX8-NEXT: s_or_b32 s2, s2, s4
; GFX8-NEXT: s_and_b32 s2, 0xffff, s2
@@ -4611,26 +4535,24 @@ define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %
; GFX8-NEXT: s_lshr_b32 s4, s3, 16
; GFX8-NEXT: s_lshl_b32 s1, s1, 1
; GFX8-NEXT: s_lshr_b32 s6, s6, 15
-; GFX8-NEXT: s_lshl_b32 s3, s3, 1
; GFX8-NEXT: s_or_b32 s1, s1, s6
; GFX8-NEXT: s_lshl_b32 s2, s2, 1
; GFX8-NEXT: s_lshr_b32 s6, s4, 15
; GFX8-NEXT: s_xor_b32 s5, s5, -1
-; GFX8-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX8-NEXT: s_bfe_u32 s3, s3, 0xf0000
; GFX8-NEXT: s_or_b32 s2, s2, s6
; GFX8-NEXT: s_lshr_b32 s6, s5, 16
; GFX8-NEXT: s_and_b32 s7, s5, 15
; GFX8-NEXT: s_andn2_b32 s5, 15, s5
-; GFX8-NEXT: s_lshr_b32 s3, s3, 1
+; GFX8-NEXT: s_and_b32 s3, 0xffff, s3
; GFX8-NEXT: s_lshl_b32 s1, s1, s7
; GFX8-NEXT: s_lshr_b32 s3, s3, s5
-; GFX8-NEXT: s_lshl_b32 s4, s4, 1
; GFX8-NEXT: s_or_b32 s1, s1, s3
; GFX8-NEXT: s_and_b32 s3, s6, 15
; GFX8-NEXT: s_lshl_b32 s2, s2, s3
-; GFX8-NEXT: s_and_b32 s3, 0xffff, s4
+; GFX8-NEXT: s_bfe_u32 s3, s4, 0xf0000
; GFX8-NEXT: s_andn2_b32 s5, 15, s6
-; GFX8-NEXT: s_lshr_b32 s3, s3, 1
+; GFX8-NEXT: s_and_b32 s3, 0xffff, s3
; GFX8-NEXT: s_lshr_b32 s3, s3, s5
; GFX8-NEXT: s_or_b32 s2, s2, s3
; GFX8-NEXT: s_and_b32 s2, 0xffff, s2
@@ -4838,61 +4760,59 @@ define <4 x half> @v_fshr_v4i16(<4 x i16> %lhs, <4 x i16> %rhs, <4 x i16> %amt)
; GFX8-LABEL: v_fshr_v4i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b16_e32 v6, 1, v0
-; GFX8-NEXT: v_lshrrev_b16_e32 v7, 15, v2
-; GFX8-NEXT: v_or_b32_e32 v6, v6, v7
-; GFX8-NEXT: v_mov_b32_e32 v7, 1
-; GFX8-NEXT: v_mov_b32_e32 v8, 15
-; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshrrev_b16_sdwa v9, v8, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_lshlrev_b16_e32 v7, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v8, 15, v2
+; GFX8-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX8-NEXT: v_mov_b32_e32 v8, 1
+; GFX8-NEXT: v_mov_b32_e32 v9, 15
; GFX8-NEXT: v_xor_b32_e32 v4, -1, v4
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v9
-; GFX8-NEXT: v_lshlrev_b16_e32 v9, 1, v2
+; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_lshrrev_b16_sdwa v10, v9, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_xor_b32_e32 v11, -1, v4
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v10
; GFX8-NEXT: v_and_b32_e32 v10, 15, v4
; GFX8-NEXT: v_and_b32_e32 v11, 15, v11
-; GFX8-NEXT: v_lshrrev_b16_e32 v9, 1, v9
-; GFX8-NEXT: v_lshlrev_b16_e32 v6, v10, v6
-; GFX8-NEXT: v_lshrrev_b16_e32 v9, v11, v9
+; GFX8-NEXT: v_bfe_u32 v2, v2, 0, 15
+; GFX8-NEXT: v_lshlrev_b16_e32 v7, v10, v7
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, v11, v2
; GFX8-NEXT: v_mov_b32_e32 v10, -1
-; GFX8-NEXT: v_lshlrev_b16_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_or_b32_e32 v6, v6, v9
-; GFX8-NEXT: v_and_b32_sdwa v9, v4, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX8-NEXT: v_and_b32_sdwa v7, v4, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_xor_b32_sdwa v4, v4, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_e32 v4, 15, v4
-; GFX8-NEXT: v_lshrrev_b16_e32 v2, 1, v2
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, v9, v0
-; GFX8-NEXT: v_lshrrev_b16_e32 v2, v4, v2
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: v_lshlrev_b16_e32 v2, 1, v1
-; GFX8-NEXT: v_lshrrev_b16_e32 v4, 15, v3
+; GFX8-NEXT: v_bfe_u32 v6, v6, 0, 15
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, v7, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v4, v4, v6
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX8-NEXT: v_or_b32_e32 v2, v2, v4
-; GFX8-NEXT: v_lshlrev_b16_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshrrev_b16_sdwa v4, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_lshlrev_b16_e32 v4, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v6, 15, v3
; GFX8-NEXT: v_xor_b32_e32 v5, -1, v5
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
-; GFX8-NEXT: v_lshlrev_b16_e32 v4, 1, v3
-; GFX8-NEXT: v_lshlrev_b16_sdwa v3, v7, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_or_b32_e32 v4, v4, v6
+; GFX8-NEXT: v_lshlrev_b16_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_lshrrev_b16_sdwa v6, v9, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_xor_b32_e32 v7, -1, v5
-; GFX8-NEXT: v_or_b32_sdwa v0, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v3
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v6
; GFX8-NEXT: v_and_b32_e32 v6, 15, v5
; GFX8-NEXT: v_and_b32_e32 v7, 15, v7
-; GFX8-NEXT: v_lshrrev_b16_e32 v4, 1, v4
-; GFX8-NEXT: v_lshlrev_b16_e32 v2, v6, v2
-; GFX8-NEXT: v_lshrrev_b16_e32 v4, v7, v4
-; GFX8-NEXT: v_or_b32_e32 v2, v2, v4
-; GFX8-NEXT: v_and_b32_sdwa v4, v5, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_bfe_u32 v3, v3, 0, 15
+; GFX8-NEXT: v_lshlrev_b16_e32 v4, v6, v4
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, v7, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX8-NEXT: v_and_b32_sdwa v4, v5, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_xor_b32_sdwa v5, v5, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_e32 v5, 15, v5
-; GFX8-NEXT: v_lshrrev_b16_e32 v3, 1, v3
+; GFX8-NEXT: v_bfe_u32 v2, v2, 0, 15
; GFX8-NEXT: v_lshlrev_b16_e32 v1, v4, v1
-; GFX8-NEXT: v_lshrrev_b16_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, v5, v2
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshr_v4i16:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir
index 0e6b692cbcfb8..f22ee6e54e977 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir
@@ -57,11 +57,15 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GCN-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; GCN-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GCN-NEXT: [[SBFX:%[0-9]+]]:_(s32) = G_SBFX [[COPY]], [[AND]](s32), [[AND1]]
- ; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SBFX]], 8
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GCN-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
+ ; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
+ ; GCN-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
+ ; GCN-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GCN-NEXT: [[SBFX:%[0-9]+]]:_(s16) = G_SBFX [[TRUNC2]], [[AND]](s16), [[AND1]]
+ ; GCN-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SBFX]](s16)
+ ; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 8
; GCN-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -86,12 +90,12 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GCN-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; GCN-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GCN-NEXT: [[SBFX:%[0-9]+]]:_(s32) = G_SBFX [[COPY]], [[AND]](s32), [[AND1]]
- ; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SBFX]], 16
- ; GCN-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
+ ; GCN-NEXT: %copy:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GCN-NEXT: %offset:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; GCN-NEXT: %width:_(s16) = G_TRUNC [[COPY2]](s32)
+ ; GCN-NEXT: %sbfx:_(s16) = G_SBFX %copy, %offset(s16), %width
+ ; GCN-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT %sbfx(s16)
+ ; GCN-NEXT: $vgpr0 = COPY [[SEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir
index 65abd75f478e6..7b26c4a4a65ed 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir
@@ -57,11 +57,16 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GCN-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; GCN-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GCN-NEXT: [[UBFX:%[0-9]+]]:_(s32) = G_UBFX [[COPY]], [[AND]](s32), [[AND1]]
- ; GCN-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UBFX]], [[C]]
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; GCN-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GCN-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
+ ; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
+ ; GCN-NEXT: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
+ ; GCN-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GCN-NEXT: [[UBFX:%[0-9]+]]:_(s16) = G_UBFX [[TRUNC2]], [[AND]](s16), [[AND1]]
+ ; GCN-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UBFX]](s16)
+ ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; GCN-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
; GCN-NEXT: $vgpr0 = COPY [[AND2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -86,12 +91,12 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GCN-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; GCN-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GCN-NEXT: [[UBFX:%[0-9]+]]:_(s32) = G_UBFX [[COPY]], [[AND]](s32), [[AND1]]
- ; GCN-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UBFX]], [[C]]
- ; GCN-NEXT: $vgpr0 = COPY [[AND2]](s32)
+ ; GCN-NEXT: %copy:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GCN-NEXT: %offset:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; GCN-NEXT: %width:_(s16) = G_TRUNC [[COPY2]](s32)
+ ; GCN-NEXT: %sbfx:_(s16) = G_UBFX %copy, %offset(s16), %width
+ ; GCN-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT %sbfx(s16)
+ ; GCN-NEXT: $vgpr0 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
index 784611cf68dd2..7d7dd85dc2451 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
@@ -38,31 +38,16 @@ define i8 @v_lshr_i8(i8 %value, i8 %amount) {
}
define i8 @v_lshr_i8_7(i8 %value) {
-; GFX6-LABEL: v_lshr_i8_7:
-; GFX6: ; %bb.0:
-; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_bfe_u32 v0, v0, 7, 1
-; GFX6-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: v_lshr_i8_7:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, 7
-; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: v_lshr_i8_7:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v1, 7
-; GFX9-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_lshr_i8_7:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_bfe_u32 v0, v0, 7, 1
+; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10PLUS-LABEL: v_lshr_i8_7:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX10PLUS-NEXT: v_lshrrev_b16 v0, 7, v0
+; GFX10PLUS-NEXT: v_bfe_u32 v0, v0, 7, 1
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = lshr i8 %value, 7
ret i8 %result
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