[llvm-branch-commits] [llvm] [AMDGPU][Legalizer] Widen i16 G_SEXT_INREG (PR #131308)

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``````````bash
git-clang-format --diff ee03ddb50d99b34981cf2cde9049829ff89a9035 815595b1ca20b613b5b4b08cafedda93e397cf92 --extensions cpp -- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 6e611ebb4b..cfb5c3b300 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2008,9 +2008,10 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
 
   // S64 is only legal on SALU, and needs to be broken into 32-bit elements in
   // RegBankSelect.
-  auto &SextInReg = getActionDefinitionsBuilder(G_SEXT_INREG)
-    .legalFor({{S32}, {S64}})
-    .widenScalarIf(typeIs(0, S16), widenScalarOrEltToNextPow2(0, 32));
+  auto &SextInReg =
+      getActionDefinitionsBuilder(G_SEXT_INREG)
+          .legalFor({{S32}, {S64}})
+          .widenScalarIf(typeIs(0, S16), widenScalarOrEltToNextPow2(0, 32));
 
   if (ST.hasVOP3PInsts()) {
     SextInReg.lowerFor({{V2S16}})

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https://github.com/llvm/llvm-project/pull/131308