[llvm-branch-commits] [llvm] [llvm] Add option to emit `callgraph` section (PR #87574)

[Matt Arsenault via llvm-branch-commits]

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@@ -0,0 +1,145 @@
+# Test MIR printer and parser for type id field in callSites. It is used
+# for propogating call site type identifiers to emit in the call graph section.
+
+# RUN: llc --call-graph-section %s -run-pass=none -o - | FileCheck %s
+# CHECK: name: main
+# CHECK: callSites:
+# CHECK-NEXT: - { bb: {{.*}}, offset: {{.*}}, fwdArgRegs: []
+# CHECK-NEXT: - { bb: {{.*}}, offset: {{.*}}, fwdArgRegs: [], typeId:
+# CHECK-NEXT: 1234567890 }
+
+--- |  
+  ; Function Attrs: mustprogress noinline nounwind optnone uwtable
+  define dso_local noundef i32 @_Z3addii(i32 noundef %a, i32 noundef %b) #0 !type !6 !type !6 {
+  entry:
+    %a.addr = alloca i32, align 4
+    %b.addr = alloca i32, align 4
+    store i32 %a, ptr %a.addr, align 4
+    store i32 %b, ptr %b.addr, align 4
+    %0 = load i32, ptr %a.addr, align 4
+    %1 = load i32, ptr %b.addr, align 4
+    %add = add nsw i32 %0, %1
+    ret i32 %add
+  }
+  
+  ; Function Attrs: mustprogress noinline nounwind optnone uwtable
+  define dso_local noundef i32 @_Z8multiplyii(i32 noundef %a, i32 noundef %b) #0 !type !6 !type !6 {
+  entry:
+    %a.addr = alloca i32, align 4
+    %b.addr = alloca i32, align 4
+    store i32 %a, ptr %a.addr, align 4
+    store i32 %b, ptr %b.addr, align 4
+    %0 = load i32, ptr %a.addr, align 4
+    %1 = load i32, ptr %b.addr, align 4
+    %mul = mul nsw i32 %0, %1
+    ret i32 %mul
+  }
+  
+  ; Function Attrs: mustprogress noinline nounwind optnone uwtable
+  define dso_local noundef ptr @_Z13get_operationb(i1 noundef zeroext %is_addition) #0 !type !7 !type !7 {
+  entry:
+    %is_addition.addr = alloca i8, align 1
+    %storedv = zext i1 %is_addition to i8
+    store i8 %storedv, ptr %is_addition.addr, align 1
+    %0 = load i8, ptr %is_addition.addr, align 1
+    %loadedv = trunc i8 %0 to i1
+    br i1 %loadedv, label %cond.true, label %cond.false
+  
+  cond.true:                                        ; preds = %entry
+    br label %cond.end
+  
+  cond.false:                                       ; preds = %entry
+    br label %cond.end
+  
+  cond.end:                                         ; preds = %cond.false, %cond.true
+    %cond = phi ptr [ @_Z3addii, %cond.true ], [ @_Z8multiplyii, %cond.false ]
+    ret ptr %cond
+  }
+  
+  ; Function Attrs: mustprogress noinline norecurse optnone uwtable
+  define dso_local noundef i32 @main(i32 noundef %argc) #1 !type !8 !type !8 {
+  entry:
+    %retval = alloca i32, align 4
+    %argc.addr = alloca i32, align 4
+    %x = alloca i32, align 4
+    %y = alloca i32, align 4
+    %op = alloca ptr, align 8
+    store i32 0, ptr %retval, align 4
+    store i32 %argc, ptr %argc.addr, align 4
+    store i32 5, ptr %x, align 4
+    store i32 10, ptr %y, align 4
+    %0 = load i32, ptr %argc.addr, align 4
+    %rem = srem i32 %0, 2
+    %cmp = icmp eq i32 %rem, 0
+    %call = call noundef ptr @_Z13get_operationb(i1 noundef zeroext %cmp) [ "callee_type"(metadata !"_ZTSFPvbE.generalized") ]
+    store ptr %call, ptr %op, align 8
+    %1 = load ptr, ptr %op, align 8
+    %2 = load i32, ptr %x, align 4
+    %3 = load i32, ptr %y, align 4
+    %call1 = call noundef i32 %1(i32 noundef %2, i32 noundef %3) [ "callee_type"(metadata !"_ZTSFiiiE.generalized") ]
+    ret i32 %call1
+  }
+  
+  attributes #0 = { mustprogress noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
+  attributes #1 = { mustprogress noinline norecurse optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
+  
+  !6 = !{i64 0, !"_ZTSFiiiE.generalized"}
+  !7 = !{i64 0, !"_ZTSFPvbE.generalized"}
+  !8 = !{i64 0, !"_ZTSFiiE.generalized"}
+
+...
+---
+name:            main
+liveins:
+  - { reg: '$edi', virtual-reg: '%0' }
+stack:
+  - { id: 0, name: retval, size: 4 }
+  - { id: 1, name: argc.addr, size: 4 }
+  - { id: 2, name: x, size: 4 }
+  - { id: 3, name: y, size: 4 }
+  - { id: 4, name: op, size: 8 }
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arsenm wrote:

Can you simplify this? I would expect you can remove everything except sample instructions that reference the callSites 

https://github.com/llvm/llvm-project/pull/87574