[llvm-branch-commits] [llvm] [SPARC][MC] Add tests for VIS family instructions (PR #130967)

[via llvm-branch-commits]

https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/130967

>From e2e0d44800b65a8fbddd6234c2ee9f83af92d7da Mon Sep 17 00:00:00 2001
From: Koakuma <koachan at protonmail.com>
Date: Wed, 12 Mar 2025 21:14:42 +0700
Subject: [PATCH 1/2] Add missing NO-VIS lines

Created using spr 1.3.5
---
 llvm/test/MC/Sparc/sparc-vis.s | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/llvm/test/MC/Sparc/sparc-vis.s b/llvm/test/MC/Sparc/sparc-vis.s
index bf01da19293d0..bed901b6a7272 100644
--- a/llvm/test/MC/Sparc/sparc-vis.s
+++ b/llvm/test/MC/Sparc/sparc-vis.s
@@ -199,28 +199,39 @@ fcmpeq16 %f0, %f2, %o0
 ! VIS: fcmpeq32 %f0, %f2, %o0                  ! encoding: [0x91,0xb0,0x05,0xc2]
 fcmpeq32 %f0, %f2, %o0
 
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
 ! VIS: edge8 %o0, %o1, %o2                     ! encoding: [0x95,0xb2,0x00,0x09]
 edge8 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
 ! VIS: edge8l %o0, %o1, %o2                    ! encoding: [0x95,0xb2,0x00,0x49]
 edge8l %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
 ! VIS: edge16 %o0, %o1, %o2                    ! encoding: [0x95,0xb2,0x00,0x89]
 edge16 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
 ! VIS: edge16l %o0, %o1, %o2                   ! encoding: [0x95,0xb2,0x00,0xc9]
 edge16l %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
 ! VIS: edge32 %o0, %o1, %o2                    ! encoding: [0x95,0xb2,0x01,0x09]
 edge32 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
 ! VIS: edge32l %o0, %o1, %o2                   ! encoding: [0x95,0xb2,0x01,0x49]
 edge32l %o0, %o1, %o2
 
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
 ! VIS: pdist %f0, %f2, %f4                     ! encoding: [0x89,0xb0,0x07,0xc2]
 pdist %f0, %f2, %f4
 
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
 ! VIS: array8 %o0, %o1, %o2                    ! encoding: [0x95,0xb2,0x02,0x09]
 array8 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
 ! VIS: array16 %o0, %o1, %o2                   ! encoding: [0x95,0xb2,0x02,0x49]
 array16 %o0, %o1, %o2
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
 ! VIS: array32 %o0, %o1, %o2                   ! encoding: [0x95,0xb2,0x02,0x89]
 array32 %o0, %o1, %o2
 
+! NO-VIS: error: instruction requires a CPU feature not currently enabled
 ! VIS: shutdown                                ! encoding: [0x81,0xb0,0x10,0x00]
 shutdown

>From b98295fcdaa9fc1d6a839956c304dd5a7d31cc24 Mon Sep 17 00:00:00 2001
From: Koakuma <koachan at protonmail.com>
Date: Wed, 12 Mar 2025 22:27:36 +0700
Subject: [PATCH 2/2] Fix typo in comment

Created using spr 1.3.5
---
 llvm/lib/Target/Sparc/SparcInstrVIS.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/Sparc/SparcInstrVIS.td b/llvm/lib/Target/Sparc/SparcInstrVIS.td
index 6d0f12da3afcf..fbf56ae22cd30 100644
--- a/llvm/lib/Target/Sparc/SparcInstrVIS.td
+++ b/llvm/lib/Target/Sparc/SparcInstrVIS.td
@@ -7,7 +7,7 @@
 //===----------------------------------------------------------------------===//
 //
 // This file contains instruction formats, definitions and patterns needed for
-// VIS, VIS II, VIS II instructions on SPARC.
+// VIS, VIS II, VIS III instructions on SPARC.
 //===----------------------------------------------------------------------===//
 
 // VIS Instruction Format.