[llvm-branch-commits] [llvm] [AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain (PR #130094)

[Matt Arsenault via llvm-branch-commits]

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@@ -116,14 +117,56 @@ static void splitBlock(MachineBasicBlock &MBB, MachineInstr &MI,
   MDT->applyUpdates(DTUpdates);
 }
 
-void SILateBranchLowering::expandChainCall(MachineInstr &MI) {
+static void addRegOrCopyOp(MachineInstrBuilder &MIB, MachineOperand &Op) {
+  if (Op.isReg())
+    MIB.addReg(Op.getReg());
+  else
+    MIB->addOperand(Op);
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arsenm wrote:

Don't understand this, the addOperand always works? MachineInstrBuilder:add is also the same as MIB->addOperand 

https://github.com/llvm/llvm-project/pull/130094