[llvm-branch-commits] [llvm] [AMDGPU] Allocate scratch space for dVGPRs for CWSR (PR #130055)

[Diana Picus via llvm-branch-commits]

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@@ -511,6 +511,14 @@ SIRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
 Register SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   const SIFrameLowering *TFI = ST.getFrameLowering();
   const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
+
+  // If we need to reserve scratch space for saving the VGPRs, then we should
+  // use the frame register for accessing our own frame (which may start at a
+  // non-zero offset).
+  if (TFI->mayReserveScratchForCWSR(MF))
+    return TFI->hasFP(MF) ? FuncInfo->getFrameOffsetReg()
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rovka wrote:

I was actually already doing that :D I cleaned this up now.

https://github.com/llvm/llvm-project/pull/130055