[llvm-branch-commits] [WIP] Introduce a G_PTRTOADDR GIsel node (PR #140300)

[Tim Gymnich via llvm-branch-commits]

================
@@ -7407,6 +7412,34 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerTRUNC(MachineInstr &MI) {
   return UnableToLegalize;
 }
 
+LegalizerHelper::LegalizeResult
+LegalizerHelper::lowerPTRTOADDR(MachineInstr &MI) {
+  // Lower G_PTRTOADDR as a truncate to address width of G_PTROINT and then
+  // zero extend to the target width if there is no native support for it.
+  MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
+  const DataLayout &DL = MIRBuilder.getDataLayout();
+  assert(MI.getOpcode() == TargetOpcode::G_PTRTOADDR);
+  auto DstReg = MI.getOperand(0).getReg();
+  auto SrcReg = MI.getOperand(1).getReg();
+  LLT SrcTy = MRI.getType(SrcReg);
+
+  LLT AddrTy = getLLTForType(
+      *DL.getAddressType(MIRBuilder.getContext(), SrcTy.getAddressSpace()), DL);
+  LLT IntPtrTy = getLLTForType(
+      *DL.getIntPtrType(MIRBuilder.getContext(), SrcTy.getAddressSpace()), DL);
+  if (SrcTy.isVector()) {
+    AddrTy = LLT::vector(SrcTy.getElementCount(), AddrTy);
+    IntPtrTy = LLT::vector(SrcTy.getElementCount(), IntPtrTy);
+  }
+  auto PtrToInt = MIRBuilder.buildPtrToInt(IntPtrTy, SrcReg);
+  auto Addr = PtrToInt;
+  if (AddrTy != IntPtrTy)
+    Addr = MIRBuilder.buildTrunc(AddrTy, PtrToInt.getReg(0));
+  MIRBuilder.buildZExtOrTrunc(DstReg, Addr.getReg(0));
----------------
tgymnich wrote:

```suggestion
  Register Addr = MIRBuilder.buildPtrToInt(IntPtrTy, SrcReg).getReg(0);
  if (AddrTy != IntPtrTy)
    Addr = MIRBuilder.buildTrunc(AddrTy,  Addr).getReg(0);
  MIRBuilder.buildZExtOrTrunc(DstReg, Addr);
```

https://github.com/llvm/llvm-project/pull/140300