[llvm-branch-commits] [GIselValueTracking] Correctly truncate/zext G_PTRTOADDR (PR #143816)

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llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-backend-amdgpu

Author: Alexander Richardson (arichardson)

<details>
<summary>Changes</summary>

G_PTRTOADDR is defined to return a zero-extended pointer address, so in
case of ptr addrspace(8) 48 bits follwed by zeroes. Fixes the
PtrToAddrExt test case in knownbits-ptrtoaddr.mir.


---
Full diff: https://github.com/llvm/llvm-project/pull/143816.diff


2 Files Affected:

- (modified) llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp (+12-1) 
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/knownbits-ptrtoaddr.mir (+1-2) 


``````````diff
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 0fe2a0955883c..cac8400e79637 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -489,9 +489,20 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
     Known = KnownBits::shl(LHSKnown, RHSKnown);
     break;
   }
+  case TargetOpcode::G_PTRTOADDR: {
+    if (DstTy.isVector())
+      break;
+    Register SrcReg = MI.getOperand(1).getReg();
+    computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);
+    unsigned PtrAS = MRI.getType(SrcReg).getAddressSpace();
+    unsigned AddrWidth = DL.getAddressSizeInBits(PtrAS);
+    if (AddrWidth < BitWidth)
+      Known = Known.trunc(AddrWidth);
+    Known = Known.zextOrTrunc(BitWidth);
+    break;
+  }
   case TargetOpcode::G_INTTOPTR:
   case TargetOpcode::G_PTRTOINT:
-  case TargetOpcode::G_PTRTOADDR:
     if (DstTy.isVector())
       break;
     // Fall through and handle them the same as zext/trunc.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/knownbits-ptrtoaddr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/knownbits-ptrtoaddr.mir
index 3fcd24ca0d031..df14fae1082ce 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/knownbits-ptrtoaddr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/knownbits-ptrtoaddr.mir
@@ -22,7 +22,6 @@ body:             |
 ...
 ---
 ## We should see 208 high zeroes followed by 48 unknown bits for extending PtrToAddr.
-## FIXME: this is currently wrong
 name:            PtrToAddrExt
 body:             |
   bb.0:
@@ -32,7 +31,7 @@ body:             |
   ; CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:1
   ; CHECK-NEXT: %3:_ KnownBits:???????????????????????????????? SignBits:1
   ; CHECK-NEXT: %4:_ KnownBits:???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? SignBits:1
-  ; CHECK-NEXT: %5:_ KnownBits:00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000???????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????? SignBits:128
+  ; CHECK-NEXT: %5:_ KnownBits:0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000???????????????????????????????????????????????? SignBits:208
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
     %2:_(s32) = COPY $vgpr2

``````````

</details>


https://github.com/llvm/llvm-project/pull/143816