[llvm-branch-commits] [CodeGen] Add 2 subtarget hooks canLowerToZeroCycleReg[Move|Zeroing] (PR #148428)

[Tomer Shafir via llvm-branch-commits]

https://github.com/tomershafir created https://github.com/llvm/llvm-project/pull/148428

Adds 2 subtarget hooks `canLowerToZeroCycleRegMove` and `canLowerToZeroCycleRegZeroing` to enable query if an instruction can be lowered to a zero cycle instruction. The logic depends on the microarchitecture. This patch also provide an implementation for AArch64 based on `AArch64InstrInfo::copyPhysReg` which supports both physical and virtual registers.

It prepares for a register coalescer optimization to prevent rematerialization of moves where the target supports ZCM.