[llvm-branch-commits] [llvm] [X86] Manage atomic load of fp -> int promotion in DAG (PR #120386)

[via llvm-branch-commits]

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@@ -2639,6 +2639,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
         setOperationAction(Op, MVT::f32, Promote);
   }
 
+  setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f16, MVT::i16);
+  setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f32, MVT::i32);
+  setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f64, MVT::i64);
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jofrn wrote:

These will still form in from `v1f16`, `v1f32`, and `v1f64`, which don't get translated in AtomicExpand. It is reachable during DAG to DAG translation. After scalarization, we promote:

1. `v1f32,ch = AtomicLoad<(load acquire (s32) from %ir.x)> t0, t2`
2. `f32,ch = AtomicLoad<(load acquire (s32) from %ir.x)> t0, t2` // scalarize
3. `i32,ch = AtomicLoad<(load acquire (s32) from %ir.x)> t0, t2` // cast

You mentioned earlier that a follow-up should have AtomicExpand's shouldCastAtomicLoadInIR return none for these; this doesn't affect these cases here though.

https://github.com/llvm/llvm-project/pull/120386