[llvm-branch-commits] [llvm] be46324 - [Hexagon] Only handle simple types memory accesses (#120654)

Tobias Hieta via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Mon Jan 13 02:52:01 PST 2025


Author: Ikhlas Ajbar
Date: 2025-01-13T11:52:22+01:00
New Revision: be46324c97a263c5c6a837317b91d818bf469266

URL: https://github.com/llvm/llvm-project/commit/be46324c97a263c5c6a837317b91d818bf469266
DIFF: https://github.com/llvm/llvm-project/commit/be46324c97a263c5c6a837317b91d818bf469266.diff

LOG: [Hexagon] Only handle simple types memory accesses (#120654)

The code was asserting because allowsMemoryAccess() was called with
Extended Value Type INVALID_SIMPLE_VALUE_TYPE in
HexagonISelLowering.cpp.
Fixes https://github.com/llvm/llvm-project/issues/118881

(cherry picked from commit 8177bf5022c6dfc48d236082fa02076feedd60df)

Added: 
    llvm/test/CodeGen/Hexagon/simple-types-mem.ll

Modified: 
    llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 7aeaebc584c64c..995c5143e0a52a 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -3796,6 +3796,8 @@ EVT HexagonTargetLowering::getOptimalMemOpType(
 bool HexagonTargetLowering::allowsMemoryAccess(
     LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
     Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const {
+  if (!VT.isSimple())
+    return false;
   MVT SVT = VT.getSimpleVT();
   if (Subtarget.isHVXVectorType(SVT, true))
     return allowsHvxMemoryAccess(SVT, Flags, Fast);
@@ -3806,6 +3808,8 @@ bool HexagonTargetLowering::allowsMemoryAccess(
 bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(
     EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
     unsigned *Fast) const {
+  if (!VT.isSimple())
+    return false;
   MVT SVT = VT.getSimpleVT();
   if (Subtarget.isHVXVectorType(SVT, true))
     return allowsHvxMisalignedMemoryAccesses(SVT, Flags, Fast);

diff  --git a/llvm/test/CodeGen/Hexagon/simple-types-mem.ll b/llvm/test/CodeGen/Hexagon/simple-types-mem.ll
new file mode 100644
index 00000000000000..01baa65a593531
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/simple-types-mem.ll
@@ -0,0 +1,22 @@
+; RUN: llc -march=hexagon < %s
+; REQUIRES: asserts
+
+; Only simple types memory accesses are handled.
+
+target triple = "hexagon"
+
+%struct.hoge = type { i320 }
+
+define dso_local void @widget() {
+bb:
+  %tmp = alloca %struct.hoge, align 1
+  %tmp1 = bitcast %struct.hoge* %tmp to i320*
+  %tmp2 = load i320, i320* %tmp1, align 1
+  %tmp3 = and i320 %tmp2, -18446744073709551616
+  %tmp4 = or i320 %tmp3, 0
+  store i320 %tmp4, i320* %tmp1, align 1
+  call void @llvm.trap()
+  unreachable
+}
+
+declare void @llvm.trap()


        


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