[llvm-branch-commits] [llvm] [SelectionDAG][X86] Split <2 x T> vector types for atomic load (PR #120640)

[via llvm-branch-commits]

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@@ -1146,6 +1146,9 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
     SplitVecRes_STEP_VECTOR(N, Lo, Hi);
     break;
   case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
+  case ISD::ATOMIC_LOAD:
+    SplitVecRes_ATOMIC_LOAD(cast<AtomicSDNode>(N), Lo, Hi);
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jofrn wrote:

After trying to coerce them via `addRegisterClass` and `setOperationPromotedToType`, it changes the what the DAG can match on, for example a non-atomic load with type `<2 x half>` is affected; so to avoid this and make the splitting valid, it now builds a vector out of the elements that are split.

https://github.com/llvm/llvm-project/pull/120640