[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Temporal divergence lowering i1 (PR #124299)

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``````````bash
git-clang-format --diff a637e5612bfe21aa7e71209ac05924309ffc9fe5 55ebcb775ada7b5401ab3ce94996690f132d89b2 --extensions cpp -- llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
index b5d3e66b05..ef4b1bd8f2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
@@ -248,13 +248,13 @@ bool DivergenceLoweringHelper::lowerTemporalDivergenceI1() {
     if (MRI->getType(Reg) != LLT::scalar(1))
       continue;
 
-    const MachineCycle * CachedLRC = LRCCache.lookup(Reg).first;
+    const MachineCycle *CachedLRC = LRCCache.lookup(Reg).first;
     if (CachedLRC) {
       LRC = CachedLRC->contains(LRC) ? CachedLRC : LRC;
       assert(LRC->contains(CachedLRC));
     }
 
-    LRCCache[Reg]={LRC, {}};
+    LRCCache[Reg] = {LRC, {}};
   }
 
   for (auto LRCIter : LRCCache) {
@@ -283,7 +283,7 @@ bool DivergenceLoweringHelper::lowerTemporalDivergenceI1() {
     buildMergeLaneMasks(*MBB, MBB->getFirstTerminator(), {}, MergedMask,
                         SSAUpdater.GetValueInMiddleOfBlock(MBB), Reg);
 
-    LRCCache[Reg].second =  MergedMask;
+    LRCCache[Reg].second = MergedMask;
   }
 
   for (auto [Reg, UseInst, Cycle] : MUI->getTemporalDivergenceList()) {

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https://github.com/llvm/llvm-project/pull/124299