[llvm-branch-commits] [llvm] release/20.x: [PowerPC] Use getSignedTargetConstant in SelectOptimalAddrMode. (#127305) (PR #127350)
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Sat Feb 15 22:12:24 PST 2025
https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/127350
>From 94291653a7414df9d825d6be9d10be345456d30c Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sat, 15 Feb 2025 14:13:32 -0800
Subject: [PATCH] [PowerPC] Use getSignedTargetConstant in
SelectOptimalAddrMode. (#127305)
Fixes #127298.
(cherry picked from commit 256145b4b0058ae22a1040cd4b7ea44fc49a4ece)
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 ++--
llvm/test/CodeGen/PowerPC/pr127298.ll | 13 +++++++++++++
2 files changed, 15 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/PowerPC/pr127298.ll
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 4ca328bd9a9ba..21ff6f050817a 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -19050,8 +19050,8 @@ PPC::AddrMode PPCTargetLowering::SelectOptimalAddrMode(const SDNode *Parent,
int32_t Addr = (int32_t)CNImm;
// Otherwise, break this down into LIS + Disp.
Disp = DAG.getSignedTargetConstant((int16_t)Addr, DL, MVT::i32);
- Base =
- DAG.getTargetConstant((Addr - (int16_t)Addr) >> 16, DL, MVT::i32);
+ Base = DAG.getSignedTargetConstant((Addr - (int16_t)Addr) >> 16, DL,
+ MVT::i32);
uint32_t LIS = CNType == MVT::i32 ? PPC::LIS : PPC::LIS8;
Base = SDValue(DAG.getMachineNode(LIS, DL, CNType, Base), 0);
break;
diff --git a/llvm/test/CodeGen/PowerPC/pr127298.ll b/llvm/test/CodeGen/PowerPC/pr127298.ll
new file mode 100644
index 0000000000000..f7560216ef7d8
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/pr127298.ll
@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=powerpc | FileCheck %s
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK: # %bb.0: # %Entry
+; CHECK-NEXT: lis 3, -8530
+; CHECK-NEXT: lbz 3, -16657(3)
+; CHECK-NEXT: blr
+Entry:
+ %0 = load volatile i8, ptr inttoptr (i32 -559038737 to ptr), align 1
+ ret void
+}
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