[llvm-branch-commits] [llvm] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)

[via llvm-branch-commits]

https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/125150

>From 259439304b31a8557db456d276a84849c7a37067 Mon Sep 17 00:00:00 2001
From: Koakuma <koachan at protonmail.com>
Date: Mon, 3 Feb 2025 23:12:07 +0700
Subject: [PATCH] Incorporate feedback

Created using spr 1.3.4
---
 llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
index 879f2ed8849618..3e9fc31d7bfc22 100644
--- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
@@ -744,7 +744,7 @@ bool SparcAsmParser::expandSETSW(MCInst &Inst, SMLoc IDLoc,
   assert(MCRegOp.isReg());
   assert(MCValOp.isImm() || MCValOp.isExpr());
 
-  // the imm operand can be either an expression or an immediate.
+  // The imm operand can be either an expression or an immediate.
   bool IsImm = Inst.getOperand(1).isImm();
   int64_t ImmValue = IsImm ? MCValOp.getImm() : 0;
   const MCExpr *ValExpr = IsImm ? MCConstantExpr::create(ImmValue, getContext())
@@ -777,7 +777,7 @@ bool SparcAsmParser::expandSETSW(MCInst &Inst, SMLoc IDLoc,
         IsSmallImm ? ValExpr
                    : adjustPICRelocation(SparcMCExpr::VK_Sparc_LO, ValExpr);
 
-    // or    rd, %lo(val), rd
+    // or rd, %lo(val), rd
     Instructions.push_back(MCInstBuilder(SP::ORri)
                                .addReg(MCRegOp.getReg())
                                .addReg(PrevReg.getReg())
@@ -790,7 +790,7 @@ bool SparcAsmParser::expandSETSW(MCInst &Inst, SMLoc IDLoc,
 
   // Large negative or non-immediate expressions would need an sra.
   if (!IsImm || ImmValue < 0) {
-    // sra    rd, %g0, rd
+    // sra rd, %g0, rd
     Instructions.push_back(MCInstBuilder(SP::SRArr)
                                .addReg(MCRegOp.getReg())
                                .addReg(MCRegOp.getReg())