[llvm-branch-commits] [llvm] CodeGen][NewPM] Port MachineScheduler to NPM. (PR #125703)

[Matt Arsenault via llvm-branch-commits]

================
@@ -384,40 +403,132 @@ nextIfDebug(MachineBasicBlock::iterator I,
       .getNonConstIterator();
 }
 
+MachineSchedulerImpl::MachineSchedulerImpl(MachineFunction &Func,
+                                           MachineFunctionPass *P)
+    : P(P) {
+  MF = &Func;
+  MLI = &P->getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+  MDT = &P->getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+  TM = &P->getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
+  AA = &P->getAnalysis<AAResultsWrapperPass>().getAAResults();
+  LIS = &P->getAnalysis<LiveIntervalsWrapperPass>().getLIS();
+}
+
+MachineSchedulerImpl::MachineSchedulerImpl(MachineFunction &Func,
+                                           MachineFunctionAnalysisManager &MFAM,
+                                           const TargetMachine *TargetM)
+    : MFAM(&MFAM) {
+  MF = &Func;
+  TM = TargetM;
+  MLI = &MFAM.getResult<MachineLoopAnalysis>(Func);
+  MDT = &MFAM.getResult<MachineDominatorTreeAnalysis>(Func);
+  auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(Func)
+                  .getManager();
+  AA = &FAM.getResult<AAManager>(Func.getFunction());
+  LIS = &MFAM.getResult<LiveIntervalsAnalysis>(Func);
+}
+
 /// Instantiate a ScheduleDAGInstrs that will be owned by the caller.
-ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() {
+ScheduleDAGInstrs *MachineSchedulerImpl::createMachineScheduler() {
   // Select the scheduler, or set the default.
   MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
   if (Ctor != useDefaultMachineSched)
     return Ctor(this);
 
-  const TargetMachine &TM =
-      getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
-
   // Get the default scheduler set by the target for this function.
-  ScheduleDAGInstrs *Scheduler = TM.createMachineScheduler(this);
+  ScheduleDAGInstrs *Scheduler = TM->createMachineScheduler(this);
   if (Scheduler)
     return Scheduler;
 
   // Default to GenericScheduler.
   return createGenericSchedLive(this);
 }
 
+bool MachineSchedulerImpl::run() {
+  if (VerifyScheduling) {
+    LLVM_DEBUG(LIS->dump());
+    std::string MSchedBanner = "Before machine scheduling.";
+    if (P)
+      MF->verify(P, MSchedBanner.c_str(), &errs());
+    else
+      MF->verify(*MFAM, MSchedBanner.c_str(), &errs());
+  }
+  RegClassInfo->runOnMachineFunction(*MF);
+
+  // Instantiate the selected scheduler for this target, function, and
+  // optimization level.
+  std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler());
+  scheduleRegions(*Scheduler, false);
+
+  LLVM_DEBUG(LIS->dump());
+  if (VerifyScheduling) {
+    std::string MSchedBanner = "After machine scheduling.";
+    if (P)
+      MF->verify(P, MSchedBanner.c_str(), &errs());
+    else
+      MF->verify(*MFAM, MSchedBanner.c_str(), &errs());
+  }
+  return true;
+}
+
+PostMachineSchedulerImpl::PostMachineSchedulerImpl(MachineFunction &Func,
+                                                   MachineFunctionPass *P)
+    : P(P) {
+  MF = &Func;
+  MLI = &P->getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+  TM = &P->getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
+  AA = &P->getAnalysis<AAResultsWrapperPass>().getAAResults();
+}
+
+PostMachineSchedulerImpl::PostMachineSchedulerImpl(
+    MachineFunction &Func, MachineFunctionAnalysisManager &MFAM,
+    const TargetMachine *TargetM)
+    : MFAM(&MFAM) {
+  MF = &Func;
+  TM = TargetM;
+  MLI = &MFAM.getResult<MachineLoopAnalysis>(Func);
+  auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(Func)
+                  .getManager();
+  AA = &FAM.getResult<AAManager>(Func.getFunction());
+}
+
 /// Instantiate a ScheduleDAGInstrs for PostRA scheduling that will be owned by
 /// the caller. We don't have a command line option to override the postRA
 /// scheduler. The Target must configure it.
-ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
-  const TargetMachine &TM =
-      getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
+ScheduleDAGInstrs *PostMachineSchedulerImpl::createPostMachineScheduler() {
   // Get the postRA scheduler set by the target for this function.
-  ScheduleDAGInstrs *Scheduler = TM.createPostMachineScheduler(this);
+  ScheduleDAGInstrs *Scheduler = TM->createPostMachineScheduler(this);
   if (Scheduler)
     return Scheduler;
 
   // Default to GenericScheduler.
   return createGenericSchedPostRA(this);
 }
 
+bool PostMachineSchedulerImpl::run() {
+  if (VerifyScheduling) {
+    std::string PostMSchedBanner = "Before post machine scheduling.";
----------------
arsenm wrote:

These can just be c strings to begin with 

https://github.com/llvm/llvm-project/pull/125703