[llvm-branch-commits] [llvm] [RISCV] Schedule RVV instructions with compatible type first (PR #95924)

[Pengcheng Wang via llvm-branch-commits]

wangpc-pp wrote:

> > * `-0.9%` of vector spills.
> > * `-1.1%` of vector reloads.
> 
> Do you know why this patch improve spills and reloads?

I was surprised by this result as well. I will do some researches and try to find some cases. But TBH, this can be a noise as register allocation is fragile and easy to be affected.

https://github.com/llvm/llvm-project/pull/95924