[llvm-branch-commits] [llvm] [RISCV] Schedule RVV instructions with compatible type first (PR #95924)

[Min-Yih Hsu via llvm-branch-commits]

https://github.com/mshockwave commented:

I'll give more detailed reviews later, just want to put some general comments first: _Ideally_, we should create a way to override `tryCandidate` in the GenericScheduler instead of forking a new scheduler, because I'm sure other targets will have a similar need. However, that requires a tons of efforts -- mostly coordinations between different targets. On the other hand, I'm now more convinced that it'll be more beneficial to the RISC-V backend if we just fork the scheduler for the time being, as it seems to be the most practical solution that allows faster iterations on RISC-V-specific scheduling ideas, which I have some on my side as well.
Therefore, I agree that we should move forward to the direction of this PR.

Could you start by tidying this up and separate the part that adds RISCVMachineScheduler into a separate PR?

https://github.com/llvm/llvm-project/pull/95924