[llvm-branch-commits] [llvm] [AArch64][SDAG] Combine INSERT_VECTOR_ELT(undef, ) -> VECTOR_SPLAT (PR #173005)

[Gaëtan Bossu via llvm-branch-commits]

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@@ -185,13 +179,7 @@ define <vscale x 16 x i8> @test_lanex_16xi8_poison(i8 %e, i32 %x) {
 define <vscale x 16 x i8> @test_lanex_16xi8_poison_imm(i8 %e, i32 %x) {
 ; CHECK-LABEL: test_lanex_16xi8_poison_imm:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.b, #0, #1
-; CHECK-NEXT:    mov w8, w1
-; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    mov z1.b, w8
-; CHECK-NEXT:    mov w8, #5 // =0x5
-; CHECK-NEXT:    cmpeq p0.b, p0/z, z0.b, z1.b
-; CHECK-NEXT:    mov z0.b, p0/m, w8
+; CHECK-NEXT:    mov z0.b, #5 // =0x5
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gbossu wrote:

Note that I haven't checked the immediate range, as I feel this should be tested in the `SPLAT_VECTOR` tests. Tbh this would be great to test the DAGCombiner independently of ISel patterns, but I don't think SDAG allows such fine-grained testing (unlike GlobalISel)

https://github.com/llvm/llvm-project/pull/173005