[llvm-branch-commits] [llvm] [DAGCombiner] Relax nsz constraint with fp->int->fp optimizations (PR #164503)

via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Tue Dec 9 04:29:30 PST 2025


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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp --diff_from_common_commit
``````````

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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 0a4353e48..1a5db5cba 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -19059,7 +19059,7 @@ static SDValue foldFPToIntToFP(SDNode *N, const SDLoc &DL, SelectionDAG &DAG,
   assert(IsSigned || IsUnsigned);
 
   bool IsSignedZeroSafe = DAG.getTarget().Options.NoSignedZerosFPMath ||
-      DAG.canIgnoreSignBitOfZero(SDValue(N, 0));
+                          DAG.canIgnoreSignBitOfZero(SDValue(N, 0));
   // For signed conversions: The optimization changes signed zero behavior.
   if (IsSigned && !IsSignedZeroSafe)
     return SDValue();

``````````

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https://github.com/llvm/llvm-project/pull/164503


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