[llvm-branch-commits] [TableGen] Slightly improve error location for a fatal error (PR #170790)

[Matt Arsenault via llvm-branch-commits]

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@@ -38,10 +59,30 @@ def PTR_ZERO_SMALL : TestInstruction {
   let opcode = 1;
   let Size = 1;
 }
-// This should fail since X0 is not necessarily part of PtrRC.
+/// This should fail since X0 is not necessarily part of PtrRC.
 def : CompressPat<(PTR_MOV PtrRC:$dst, X0),
                   (PTR_ZERO_SMALL PtrRC:$dst)>;
 // CHECK: [[#@LINE-2]]:1: error: cannot resolve HwMode for PtrRC
-// CHECK: Common.td:6:5: note: PtrRC defined here
+// CHECK: Common.td:7:5: note: PtrRC defined here
 def MyTargetISA : InstrInfo;
 def MyTarget : Target { let InstructionSet = MyTargetISA; }
+
+
+//--- compress-regclass-by-hwmode-2.td
+include "Common.td"
+def X_MOV_BIG : TestInstruction {
+  let OutOperandList = (outs XRegs:$dst);
+  let InOperandList = (ins XRegs:$src);
+  let AsmString = "x_mov $dst, $src";
+  let opcode = 1;
+  let Size = 4;
+}
+/// This should fail since PtrRC is not necessarily part of XRegs.
+/// In theory, this could be resolved depending on the Predicates but
+/// for not we should just always emit an error.
+let Predicates = [IsPtr32] in
+def : CompressPat<(X_MOV_BIG XRegs:$dst, XRegs:$src),
+                  (PTR_MOV PtrRC:$dst, PtrRC:$src)>;
+// CHECK: [[#@LINE-2]]:1: error: Type mismatch between Input and Output Dag operand 'dst'
+def MyTargetISA : InstrInfo;
+def MyTarget : Target { let InstructionSet = MyTargetISA; }
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arsenm wrote:

End of file new line error 

https://github.com/llvm/llvm-project/pull/170790