[llvm-branch-commits] [llvm] 2e2eea7 - Revert "[RISCV] Use GPRNoX0 instead of AVL for Xsfmm pseudos. NFC (#170726)"

[via llvm-branch-commits]

Author: Craig Topper
Date: 2025-12-07T22:50:15-08:00
New Revision: 2e2eea73f6a1a48978d54400ede4ae905d1bcf6d

URL: https://github.com/llvm/llvm-project/commit/2e2eea73f6a1a48978d54400ede4ae905d1bcf6d
DIFF: https://github.com/llvm/llvm-project/commit/2e2eea73f6a1a48978d54400ede4ae905d1bcf6d.diff

LOG: Revert "[RISCV] Use GPRNoX0 instead of AVL for Xsfmm pseudos. NFC (#170726)"

This reverts commit 446a3a19ed93449a9b50533f924f4bb658fd113e.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td
index 445e513d36a38..a3e02ee4fc430 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td
@@ -278,7 +278,7 @@ let Uses = [FRM], mayRaiseFPException = true in {
 } // DecoderNamespace = "XSfvector"
 
 class VPseudoSF_VTileLoad
-    : RISCVVPseudo<(outs), (ins GPR:$rs2, GPR:$rs1, GPRNoX0:$atn, ixlenimm:$sew,
+    : RISCVVPseudo<(outs), (ins GPR:$rs2, GPR:$rs1, AVL:$atn, ixlenimm:$sew,
                                 ixlenimm:$twiden)> {
   let mayLoad = 1;
   let mayStore = 0;
@@ -289,7 +289,7 @@ class VPseudoSF_VTileLoad
 }
 
 class VPseudoSF_VTileStore
-    : RISCVVPseudo<(outs), (ins GPR:$rs2, GPR:$rs1, GPRNoX0:$atn, ixlenimm:$sew,
+    : RISCVVPseudo<(outs), (ins GPR:$rs2, GPR:$rs1, AVL:$atn, ixlenimm:$sew,
                                 ixlenimm:$twiden)> {
   let mayLoad = 0;
   let mayStore = 1;
@@ -300,7 +300,7 @@ class VPseudoSF_VTileStore
 }
 
 class VPseudoSF_VTileMove_V_T
-    : RISCVVPseudo<(outs VRM8:$vd), (ins GPR:$rs1, GPRNoX0:$atn, ixlenimm:$sew,
+    : RISCVVPseudo<(outs VRM8:$vd), (ins GPR:$rs1, AVL:$atn, ixlenimm:$sew,
                                          ixlenimm:$twiden)> {
   let mayLoad = 0;
   let mayStore = 0;
@@ -311,7 +311,7 @@ class VPseudoSF_VTileMove_V_T
 }
 
 class VPseudoSF_VTileMove_T_V
-    : RISCVVPseudo<(outs), (ins GPR:$rs1, VRM8:$vs2, GPRNoX0:$atn, ixlenimm:$sew,
+    : RISCVVPseudo<(outs), (ins GPR:$rs1, VRM8:$vs2, AVL:$atn, ixlenimm:$sew,
                                 ixlenimm:$twiden)> {
   let mayLoad = 0;
   let mayStore = 0;
@@ -323,9 +323,8 @@ class VPseudoSF_VTileMove_T_V
 
 class VPseudoSF_MatMul<RegisterClass mtd_class>
     : RISCVVPseudo<(outs),
-                   (ins mtd_class:$rd, VRM8:$vs2, VRM8:$vs1, GPRNoX0:$atm,
-                        GPRNoX0:$atn, GPRNoX0:$atk, ixlenimm:$sew,
-                        ixlenimm:$twiden)> {
+                   (ins mtd_class:$rd, VRM8:$vs2, VRM8:$vs1, AVL:$atm, AVL:$atn,
+                        AVL:$atk, ixlenimm:$sew, ixlenimm:$twiden)> {
   let mayLoad = 0;
   let mayStore = 0;
   let HasTmOp = 1;
@@ -339,7 +338,7 @@ class VPseudoSF_MatMul<RegisterClass mtd_class>
 class VPseudoSF_MatMul_FRM<RegisterClass mtd_class>
     : RISCVVPseudo<(outs),
                    (ins mtd_class:$rd, VRM8:$vs2, VRM8:$vs1, ixlenimm:$frm,
-                        GPRNoX0:$atm, GPRNoX0:$atn, GPRNoX0:$atk, ixlenimm:$sew,
+                        AVL:$atm, AVL:$atn, AVL:$atk, ixlenimm:$sew,
                         ixlenimm:$twiden), []> {
   let mayLoad = 0;
   let mayStore = 0;
@@ -414,7 +413,7 @@ let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
   let HasVLOp = 1, HasTmOp = 1, HasTWidenOp = 1, HasSEWOp = 1 in
     def PseudoSF_VTZERO_T
         : RISCVVPseudo<(outs),
-                       (ins TR:$rd, GPRNoX0:$atm, GPRNoX0:$atn, ixlenimm:$sew,
+                       (ins TR:$rd, AVL:$atm, AVL:$atn, ixlenimm:$sew,
                             ixlenimm:$twiden)>;
   def PseudoSF_VTDISCARD : RISCVVPseudo<(outs), (ins), []>;
 }
@@ -425,7 +424,7 @@ class VPatXSfmmTileStore<string intrinsic_name,
   Pat<(!cast<Intrinsic>(intrinsic_name)
        (XLenVT GPR:$rs2),
        (XLenVT GPR:$rs1),
-       (XLenVT GPRNoX0:$tn)),
+       (XLenVT AVL:$tn)),
       (!cast<Instruction>(inst_name)
        (XLenVT GPR:$rs2),
        (XLenVT GPR:$rs1),
@@ -438,7 +437,7 @@ class VPatXSfmmTileMove_T_V<string intrinsic_name,
   Pat<(!cast<Intrinsic>(intrinsic_name)
                     (XLenVT GPR:$rs1),
                     (reg_type VRM8:$vs2),
-                    (XLenVT GPRNoX0:$atn)),
+                    (XLenVT AVL:$atn)),
       (!cast<Instruction>(inst_name)
        (XLenVT GPR:$rs1),
        (reg_type VRM8:$vs2),
@@ -450,7 +449,7 @@ class VPatXSfmmTileMove_V_T<string intrinsic_name,
                             int log2sew> :
   Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
                     (XLenVT GPR:$rs1),
-                    (XLenVT GPRNoX0:$atn))),
+                    (XLenVT AVL:$atn))),
       (!cast<Instruction>(inst_name)
        (XLenVT GPR:$rs1),
        GPR:$atn, log2sew, 1)>;