[llvm-branch-commits] [llvm] Users/ppenzin/ra saverestore split calleesaves (PR #170609)

[via llvm-branch-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/include/llvm/CodeGen/TargetFrameLowering.h llvm/include/llvm/CodeGen/TargetRegisterInfo.h llvm/include/llvm/CodeGen/TargetSubtargetInfo.h llvm/lib/CodeGen/PrologEpilogInserter.cpp llvm/lib/CodeGen/RegisterScavenging.cpp llvm/lib/CodeGen/ShrinkWrap.cpp llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp llvm/lib/Target/AArch64/AArch64FrameLowering.cpp llvm/lib/Target/AArch64/AArch64FrameLowering.h llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h llvm/lib/Target/AMDGPU/SIFrameLowering.cpp llvm/lib/Target/AMDGPU/SIFrameLowering.h llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp llvm/lib/Target/ARC/ARCFrameLowering.cpp llvm/lib/Target/ARC/ARCFrameLowering.h llvm/lib/Target/ARM/ARMFrameLowering.cpp llvm/lib/Target/ARM/ARMFrameLowering.h llvm/lib/Target/ARM/ARMMachineFunctionInfo.h llvm/lib/Target/AVR/AVRFrameLowering.cpp llvm/lib/Target/AVR/AVRFrameLowering.h llvm/lib/Target/BPF/BPFFrameLowering.cpp llvm/lib/Target/BPF/BPFFrameLowering.h llvm/lib/Target/CSKY/CSKYFrameLowering.cpp llvm/lib/Target/CSKY/CSKYFrameLowering.h llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp llvm/lib/Target/Hexagon/HexagonFrameLowering.h llvm/lib/Target/Lanai/LanaiFrameLowering.cpp llvm/lib/Target/Lanai/LanaiFrameLowering.h llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp llvm/lib/Target/LoongArch/LoongArchFrameLowering.h llvm/lib/Target/M68k/M68kFrameLowering.cpp llvm/lib/Target/M68k/M68kFrameLowering.h llvm/lib/Target/Mips/Mips16FrameLowering.cpp llvm/lib/Target/Mips/Mips16FrameLowering.h llvm/lib/Target/Mips/MipsSEFrameLowering.cpp llvm/lib/Target/Mips/MipsSEFrameLowering.h llvm/lib/Target/PowerPC/PPCFrameLowering.cpp llvm/lib/Target/PowerPC/PPCFrameLowering.h llvm/lib/Target/RISCV/RISCVFrameLowering.cpp llvm/lib/Target/RISCV/RISCVFrameLowering.h llvm/lib/Target/RISCV/RISCVSubtarget.cpp llvm/lib/Target/RISCV/RISCVSubtarget.h llvm/lib/Target/Sparc/SparcFrameLowering.cpp llvm/lib/Target/Sparc/SparcFrameLowering.h llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp llvm/lib/Target/SystemZ/SystemZFrameLowering.h llvm/lib/Target/VE/VEFrameLowering.cpp llvm/lib/Target/VE/VEFrameLowering.h llvm/lib/Target/X86/X86FrameLowering.cpp llvm/lib/Target/X86/X86FrameLowering.h llvm/lib/Target/XCore/XCoreFrameLowering.cpp llvm/lib/Target/XCore/XCoreFrameLowering.h llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp llvm/lib/Target/Xtensa/XtensaFrameLowering.h --diff_from_common_commit
``````````

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index f78037545..e56e6125e 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -34,8 +34,9 @@ using namespace llvm;
 
 static cl::opt<std::string> UserDefinedUncondPrologCSRs(
     "riscv-user-defined-uncond-prolog-csrs",
-    cl::desc("Comma-separated list of registerst that have to be saved / restored in prolog / epilog. Used for testing only"), cl::init(""),
-    cl::Hidden);
+    cl::desc("Comma-separated list of registerst that have to be saved / "
+             "restored in prolog / epilog. Used for testing only"),
+    cl::init(""), cl::Hidden);
 
 static Align getABIStackAlignment(RISCVABI::ABI ABI) {
   if (ABI == RISCVABI::ABI_ILP32E)
@@ -1535,7 +1536,9 @@ static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI,
 #define GET_REGISTER_MATCHER
 #include "RISCVGenAsmMatcher.inc"
 
-void RISCVFrameLowering::determineUncondPrologCalleeSaves(MachineFunction &MF, const MCPhysReg *CSRegs, BitVector &UncondPrologCSRs) const {
+void RISCVFrameLowering::determineUncondPrologCalleeSaves(
+    MachineFunction &MF, const MCPhysReg *CSRegs,
+    BitVector &UncondPrologCSRs) const {
   const RISCVRegisterInfo *TRI = STI.getRegisterInfo();
 
   StringRef RegString(UserDefinedUncondPrologCSRs);
@@ -1554,17 +1557,18 @@ void RISCVFrameLowering::determineUncondPrologCalleeSaves(MachineFunction &MF, c
     UncondPrologCSRs.set(Reg.id());
   }
 
-  TargetFrameLowering::determineUncondPrologCalleeSaves(MF, CSRegs, UncondPrologCSRs);
+  TargetFrameLowering::determineUncondPrologCalleeSaves(MF, CSRegs,
+                                                        UncondPrologCSRs);
 }
 
 void RISCVFrameLowering::determinePrologCalleeSaves(MachineFunction &MF,
-                                              BitVector &SavedRegs,
-                                              RegScavenger *RS) const {
+                                                    BitVector &SavedRegs,
+                                                    RegScavenger *RS) const {
   TargetFrameLowering::determinePrologCalleeSaves(MF, SavedRegs, RS);
 
-  // In TargetFrameLowering::determinePrologCalleeSaves, any vector register is marked
-  // as saved if any of its subregister is clobbered, this is not correct in
-  // vector registers. We only want the vector register to be marked as saved
+  // In TargetFrameLowering::determinePrologCalleeSaves, any vector register is
+  // marked as saved if any of its subregister is clobbered, this is not correct
+  // in vector registers. We only want the vector register to be marked as saved
   // if all of its subregisters are clobbered.
   // For example:
   // Original behavior: If v24 is marked, v24m2, v24m4, v24m8 are also marked.
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.h b/llvm/lib/Target/RISCV/RISCVFrameLowering.h
index b1835877e..292105ef6 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.h
@@ -34,10 +34,12 @@ public:
   StackOffset getFrameIndexReference(const MachineFunction &MF, int FI,
                                      Register &FrameReg) const override;
 
-  void determineUncondPrologCalleeSaves(MachineFunction &MF, const MCPhysReg *CSRegs, BitVector &UncondPrologCSRs) const override;
+  void
+  determineUncondPrologCalleeSaves(MachineFunction &MF, const MCPhysReg *CSRegs,
+                                   BitVector &UncondPrologCSRs) const override;
 
   void determinePrologCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
-                            RegScavenger *RS) const override;
+                                  RegScavenger *RS) const override;
 
   void processFunctionBeforeFrameFinalized(MachineFunction &MF,
                                            RegScavenger *RS) const override;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 3dcad5273..5a0f9421b 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -76,8 +76,8 @@ static cl::opt<bool> EnablePExtCodeGen(
     cl::init(false), cl::Hidden);
 
 static cl::opt<bool> SaveCSREarly("riscv-save-csrs-early",
-                                  cl::desc("Save CSRs early"),
-                                  cl::init(false), cl::Hidden);
+                                  cl::desc("Save CSRs early"), cl::init(false),
+                                  cl::Hidden);
 
 void RISCVSubtarget::anchor() {}
 
@@ -270,6 +270,4 @@ bool RISCVSubtarget::useMIPSCCMovInsn() const {
   return UseMIPSCCMovInsn && HasVendorXMIPSCMov;
 }
 
-bool RISCVSubtarget::savesCSRsEarly() const {
-  return SaveCSREarly;
-}
+bool RISCVSubtarget::savesCSRsEarly() const { return SaveCSREarly; }

``````````

</details>


https://github.com/llvm/llvm-project/pull/170609