[llvm-branch-commits] [llvm] [AMDGPU] Update GCNHazardRecognizer's understanding of gfx12 waitcount instructions (PR #153880)

[Stanislav Mekhanoshin via llvm-branch-commits]

https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/153880

This simply updates the pass's cognizance of these instructions, and for the
most part the hazards where they might be encountered do not exist for gfx12.
Nonetheless, encountering them has to be checked for as doing so would indicate
a compiler error.

Co-authored-by: Stephen Thomas <Stephen.Thomas at amd.com>

>From 2f96c402497f80f8d31e4229f03b3ef8dd88cf4d Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: Fri, 15 Aug 2025 14:10:55 -0700
Subject: [PATCH] [AMDGPU] Update GCNHazardRecognizer's understanding of gfx12
 waitcount instructions

This simply updates the pass's cognizance of these instructions, and for the
most part the hazards where they might be encountered do not exist for gfx12.
Nonetheless, encountering them has to be checked for as doing so would indicate
a compiler error.

Co-authored-by: Stephen Thomas <Stephen.Thomas at amd.com>
---
 .../lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index c1cca063aac6f..fa3ca27a5f47c 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -1357,6 +1357,16 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) {
         // DsCnt corresponds to LGKMCnt here.
         return (Decoded.DsCnt == 0);
       }
+      case AMDGPU::S_WAIT_STORECNT:
+      case AMDGPU::S_WAIT_STORECNT_DSCNT:
+      case AMDGPU::S_WAIT_LOADCNT:
+      case AMDGPU::S_WAIT_LOADCNT_DSCNT:
+      case AMDGPU::S_WAIT_SAMPLECNT:
+      case AMDGPU::S_WAIT_BVHCNT:
+      case AMDGPU::S_WAIT_DSCNT:
+      case AMDGPU::S_WAIT_EXPCNT:
+      case AMDGPU::S_WAIT_KMCNT:
+        llvm_unreachable("unexpected wait count instruction");
       default:
         // SOPP instructions cannot mitigate the hazard.
         if (TII->isSOPP(MI))
@@ -2254,6 +2264,15 @@ int GCNHazardRecognizer::checkFPAtomicToDenormModeHazard(MachineInstr *MI) {
     case AMDGPU::S_WAITCNT_EXPCNT:
     case AMDGPU::S_WAITCNT_LGKMCNT:
     case AMDGPU::S_WAIT_IDLE:
+    case AMDGPU::S_WAIT_LOADCNT:
+    case AMDGPU::S_WAIT_LOADCNT_DSCNT:
+    case AMDGPU::S_WAIT_SAMPLECNT:
+    case AMDGPU::S_WAIT_BVHCNT:
+    case AMDGPU::S_WAIT_STORECNT:
+    case AMDGPU::S_WAIT_STORECNT_DSCNT:
+    case AMDGPU::S_WAIT_EXPCNT:
+    case AMDGPU::S_WAIT_DSCNT:
+    case AMDGPU::S_WAIT_KMCNT:
       return true;
     default:
       break;