[llvm-branch-commits] [llvm] [AMDGPU][UnifyDivergentExitNodes][StructurizeCFG] Add support for callbr instruction with inline-asm (PR #152161)

[Robert Imschweiler via llvm-branch-commits]

ro-i wrote:

@ruiling You can find most of the rationale behind this in https://discourse.llvm.org/t/rfc-add-callbr-intrinsic-support/86087 and the PR that is adding support for callbr+intrinsics: https://github.com/llvm/llvm-project/pull/133907.
In short:
> do you plan to support arbitrary form of callbr, or only very limited form?

very limited, only for selected intrinsics, such as llvm.amdgcn.kill

> What is the expected use case?

Being able to explicitly show the semantics of control-flow manipulating intrinsics, such as kill, which either continues execution without doing anything or basically directly leads to unreachable (since IR is representing a single lane).

> How would callbr be lowered in the backend?

Not at all. It only serves as an improvement of the IR handling. For the resulting assembly, there mostly won't/shouldn't be any differences. At least for my implementation of callbr+amdgcn.kill, the assembly stayed the same. See https://github.com/llvm/llvm-project/pull/133907/files#diff-9a591a6648d6c195914e07f22aae2329611e8c7de5ca5968412c4341e62d8d23 (this link will probably become invalid if I have to rebase that PR again).

> (I mean how the wave-execution would be look like if different threads went to different labels?)

see above. kill and callbr+kill are no different in that the thread is either continuing execution or become dead.

https://github.com/llvm/llvm-project/pull/152161