[llvm-branch-commits] [llvm] [AArch64][ISel] Extend vector_splice tests (NFC) (PR #152553)
Gaëtan Bossu via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Aug 7 10:17:53 PDT 2025
https://github.com/gbossu created https://github.com/llvm/llvm-project/pull/152553
They use extract shuffles for fixed vectors, and
llvm.vector.splice intrinsics for scalable vectors.
In the previous tests using ld+extract+st, the extract was optimized away and replaced by a smaller load at the right offset. This meant we didin't really test the vector_splice ISD node.
**This is a chained PR**
>From a6be08b2dd026b6b3dcd7ca8ed5e231671a160b3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ga=C3=ABtan=20Bossu?= <gaetan.bossu at arm.com>
Date: Wed, 6 Aug 2025 10:32:44 +0000
Subject: [PATCH] [AArch64][ISel] Extend vector_splice tests (NFC)
They use extract shuffles for fixed vectors, and
llvm.vector.splice intrinsics for scalable vectors.
In the previous tests using ld+extract+st, the extract was optimized
away and replaced by a smaller load at the right offset. This meant
we didin't really test the vector_splice ISD node.
---
.../sve-fixed-length-extract-subvector.ll | 368 +++++++++++++++++-
.../test/CodeGen/AArch64/sve-vector-splice.ll | 162 ++++++++
2 files changed, 526 insertions(+), 4 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/sve-vector-splice.ll
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
index 00002dd3269a2..800f95d97af4c 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
@@ -5,6 +5,12 @@
target triple = "aarch64-unknown-linux-gnu"
+; Note that both the vector.extract intrinsics and SK_ExtractSubvector
+; shufflevector instructions get detected as a extract_subvector ISD node in
+; SelectionDAG. We'll test both cases for the sake of completeness, even though
+; vector.extract intrinsics should get lowered into shufflevector by the time we
+; reach the backend.
+
; i8
; Don't use SVE for 64-bit vectors.
@@ -40,6 +46,67 @@ define void @extract_subvector_v32i8(ptr %a, ptr %b) vscale_range(2,0) #0 {
ret void
}
+define void @extract_v32i8_halves(ptr %in, ptr %out, ptr %out2) #0 vscale_range(2,2) {
+; CHECK-LABEL: extract_v32i8_halves:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: str q1, [x1]
+; CHECK-NEXT: str q0, [x2]
+; CHECK-NEXT: ret
+entry:
+ %b = load <32 x i8>, ptr %in
+ %hi = shufflevector <32 x i8> %b, <32 x i8> poison, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+ store <16 x i8> %hi, ptr %out
+ %lo = shufflevector <32 x i8> %b, <32 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ store <16 x i8> %lo, ptr %out2
+ ret void
+}
+
+define void @extract_v32i8_half_unaligned(ptr %in, ptr %out) #0 vscale_range(2,2) {
+; CHECK-LABEL: extract_v32i8_half_unaligned:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #4
+; CHECK-NEXT: str q0, [x1]
+; CHECK-NEXT: ret
+entry:
+ %b = load <32 x i8>, ptr %in
+ %d = shufflevector <32 x i8> %b, <32 x i8> poison, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
+ store <16 x i8> %d, ptr %out
+ ret void
+}
+
+define void @extract_v32i8_quarters(ptr %in, ptr %out, ptr %out2, ptr %out3, ptr %out4) #0 vscale_range(2,2) {
+; CHECK-LABEL: extract_v32i8_quarters:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: mov z2.d, z0.d
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: ext z2.b, z2.b, z0.b, #24
+; CHECK-NEXT: str d1, [x1]
+; CHECK-NEXT: str d2, [x2]
+; CHECK-NEXT: str d0, [x3]
+; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
+; CHECK-NEXT: str d0, [x4]
+; CHECK-NEXT: ret
+entry:
+ %b = load <32 x i8>, ptr %in
+ %hilo = shufflevector <32 x i8> %b, <32 x i8> poison, <8 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
+ store <8 x i8> %hilo, ptr %out
+ %hihi = shufflevector <32 x i8> %b, <32 x i8> poison, <8 x i32> <i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+ store <8 x i8> %hihi, ptr %out2
+ %lolo = shufflevector <32 x i8> %b, <32 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ store <8 x i8> %lolo, ptr %out3
+ %lohi = shufflevector <32 x i8> %b, <32 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ store <8 x i8> %lohi, ptr %out4
+ ret void
+}
+
define void @extract_subvector_v64i8(ptr %a, ptr %b) #0 {
; CHECK-LABEL: extract_subvector_v64i8:
; CHECK: // %bb.0:
@@ -54,6 +121,25 @@ define void @extract_subvector_v64i8(ptr %a, ptr %b) #0 {
ret void
}
+define void @extract_v64i8_halves(ptr %in, ptr %out, ptr %out2) #0 vscale_range(4,4) {
+; CHECK-LABEL: extract_v64i8_halves:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: ptrue p0.b, vl32
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #32
+; CHECK-NEXT: st1b { z1.b }, p0, [x1]
+; CHECK-NEXT: st1b { z0.b }, p0, [x2]
+; CHECK-NEXT: ret
+entry:
+ %b = load <64 x i8>, ptr %in
+ %hi = shufflevector <64 x i8> %b, <64 x i8> poison, <32 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
+ store <32 x i8> %hi, ptr %out
+ %lo = shufflevector <64 x i8> %b, <64 x i8> poison, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+ store <32 x i8> %lo, ptr %out2
+ ret void
+}
+
define void @extract_subvector_v128i8(ptr %a, ptr %b) vscale_range(8,0) #0 {
; CHECK-LABEL: extract_subvector_v128i8:
; CHECK: // %bb.0:
@@ -117,6 +203,24 @@ define void @extract_subvector_v16i16(ptr %a, ptr %b) vscale_range(2,0) #0 {
ret void
}
+define void @extract_v16i16_halves(ptr %in, ptr %out, ptr %out2) #0 vscale_range(2,2) {
+; CHECK-LABEL: extract_v16i16_halves:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: str q1, [x1]
+; CHECK-NEXT: str q0, [x2]
+; CHECK-NEXT: ret
+entry:
+ %b = load <16 x i16>, ptr %in
+ %hi = shufflevector <16 x i16> %b, <16 x i16> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ store <8 x i16> %hi, ptr %out
+ %lo = shufflevector <16 x i16> %b, <16 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ store <8 x i16> %lo, ptr %out2
+ ret void
+}
+
define void @extract_subvector_v32i16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: extract_subvector_v32i16:
; CHECK: // %bb.0:
@@ -131,6 +235,25 @@ define void @extract_subvector_v32i16(ptr %a, ptr %b) #0 {
ret void
}
+define void @extract_v32i16_halves(ptr %in, ptr %out, ptr %out2) #0 vscale_range(4,4) {
+; CHECK-LABEL: extract_v32i16_halves:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: ptrue p0.h, vl16
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #32
+; CHECK-NEXT: st1h { z1.h }, p0, [x1]
+; CHECK-NEXT: st1h { z0.h }, p0, [x2]
+; CHECK-NEXT: ret
+entry:
+ %b = load <32 x i16>, ptr %in
+ %hi = shufflevector <32 x i16> %b, <32 x i16> poison, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+ store <16 x i16> %hi, ptr %out
+ %lo = shufflevector <32 x i16> %b, <32 x i16> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ store <16 x i16> %lo, ptr %out2
+ ret void
+}
+
define void @extract_subvector_v64i16(ptr %a, ptr %b) vscale_range(8,0) #0 {
; CHECK-LABEL: extract_subvector_v64i16:
; CHECK: // %bb.0:
@@ -195,6 +318,24 @@ define void @extract_subvector_v8i32(ptr %a, ptr %b) vscale_range(2,0) #0 {
ret void
}
+define void @extract_v8i32_halves(ptr %in, ptr %out, ptr %out2) #0 vscale_range(2,2) {
+; CHECK-LABEL: extract_v8i32_halves:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: str q1, [x1]
+; CHECK-NEXT: str q0, [x2]
+; CHECK-NEXT: ret
+entry:
+ %b = load <8 x i32>, ptr %in
+ %hi = shufflevector <8 x i32> %b, <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ store <4 x i32> %hi, ptr %out
+ %lo = shufflevector <8 x i32> %b, <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ store <4 x i32> %lo, ptr %out2
+ ret void
+}
+
define void @extract_subvector_v16i32(ptr %a, ptr %b) #0 {
; CHECK-LABEL: extract_subvector_v16i32:
; CHECK: // %bb.0:
@@ -209,6 +350,25 @@ define void @extract_subvector_v16i32(ptr %a, ptr %b) #0 {
ret void
}
+define void @extract_v16i32_halves(ptr %in, ptr %out, ptr %out2) #0 vscale_range(4,4) {
+; CHECK-LABEL: extract_v16i32_halves:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: ptrue p0.s, vl8
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #32
+; CHECK-NEXT: st1w { z1.s }, p0, [x1]
+; CHECK-NEXT: st1w { z0.s }, p0, [x2]
+; CHECK-NEXT: ret
+entry:
+ %b = load <16 x i32>, ptr %in
+ %hi = shufflevector <16 x i32> %b, <16 x i32> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ store <8 x i32> %hi, ptr %out
+ %lo = shufflevector <16 x i32> %b, <16 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ store <8 x i32> %lo, ptr %out2
+ ret void
+}
+
define void @extract_subvector_v32i32(ptr %a, ptr %b) vscale_range(8,0) #0 {
; CHECK-LABEL: extract_subvector_v32i32:
; CHECK: // %bb.0:
@@ -262,6 +422,24 @@ define void @extract_subvector_v4i64(ptr %a, ptr %b) vscale_range(2,0) #0 {
ret void
}
+define void @extract_v4i64_halves(ptr %in, ptr %out, ptr %out2) #0 vscale_range(2,2) {
+; CHECK-LABEL: extract_v4i64_halves:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: str q1, [x1]
+; CHECK-NEXT: str q0, [x2]
+; CHECK-NEXT: ret
+entry:
+ %b = load <4 x i64>, ptr %in
+ %hi = shufflevector <4 x i64> %b, <4 x i64> poison, <2 x i32> <i32 2, i32 3>
+ store <2 x i64> %hi, ptr %out
+ %lo = shufflevector <4 x i64> %b, <4 x i64> poison, <2 x i32> <i32 0, i32 1>
+ store <2 x i64> %lo, ptr %out2
+ ret void
+}
+
define void @extract_subvector_v8i64(ptr %a, ptr %b) vscale_range(2,0) #0 {
; CHECK-LABEL: extract_subvector_v8i64:
; CHECK: // %bb.0:
@@ -276,6 +454,25 @@ define void @extract_subvector_v8i64(ptr %a, ptr %b) vscale_range(2,0) #0 {
ret void
}
+define void @extract_v8i64_halves(ptr %in, ptr %out, ptr %out2) #0 vscale_range(4,4) {
+; CHECK-LABEL: extract_v8i64_halves:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #32
+; CHECK-NEXT: st1d { z1.d }, p0, [x1]
+; CHECK-NEXT: st1d { z0.d }, p0, [x2]
+; CHECK-NEXT: ret
+entry:
+ %b = load <8 x i64>, ptr %in
+ %hi = shufflevector <8 x i64> %b, <8 x i64> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ store <4 x i64> %hi, ptr %out
+ %lo = shufflevector <8 x i64> %b, <8 x i64> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ store <4 x i64> %lo, ptr %out2
+ ret void
+}
+
define void @extract_subvector_v16i64(ptr %a, ptr %b) #0 {
; VBITS_GE_256-LABEL: extract_subvector_v16i64:
; VBITS_GE_256: // %bb.0:
@@ -352,6 +549,24 @@ define void @extract_subvector_v16f16(ptr %a, ptr %b) vscale_range(2,0) #0 {
ret void
}
+define void @extract_v16half_halves(ptr %in, ptr %out, ptr %out2) #0 vscale_range(2,2) {
+; CHECK-LABEL: extract_v16half_halves:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: str q1, [x1]
+; CHECK-NEXT: str q0, [x2]
+; CHECK-NEXT: ret
+entry:
+ %b = load <16 x half>, ptr %in
+ %hi = shufflevector <16 x half> %b, <16 x half> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ store <8 x half> %hi, ptr %out
+ %lo = shufflevector <16 x half> %b, <16 x half> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ store <8 x half> %lo, ptr %out2
+ ret void
+}
+
define void @extract_subvector_v32f16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: extract_subvector_v32f16:
; CHECK: // %bb.0:
@@ -366,6 +581,25 @@ define void @extract_subvector_v32f16(ptr %a, ptr %b) #0 {
ret void
}
+define void @extract_v32half_halves(ptr %in, ptr %out, ptr %out2) #0 vscale_range(4,4) {
+; CHECK-LABEL: extract_v32half_halves:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: ptrue p0.h, vl16
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #32
+; CHECK-NEXT: st1h { z1.h }, p0, [x1]
+; CHECK-NEXT: st1h { z0.h }, p0, [x2]
+; CHECK-NEXT: ret
+entry:
+ %b = load <32 x half>, ptr %in
+ %hi = shufflevector <32 x half> %b, <32 x half> poison, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+ store <16 x half> %hi, ptr %out
+ %lo = shufflevector <32 x half> %b, <32 x half> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ store <16 x half> %lo, ptr %out2
+ ret void
+}
+
define void @extract_subvector_v64f16(ptr %a, ptr %b) vscale_range(8,0) #0 {
; CHECK-LABEL: extract_subvector_v64f16:
; CHECK: // %bb.0:
@@ -430,6 +664,24 @@ define void @extract_subvector_v8f32(ptr %a, ptr %b) vscale_range(2,0) #0 {
ret void
}
+define void @extract_v8float_halves(ptr %in, ptr %out, ptr %out2) #0 vscale_range(2,2) {
+; CHECK-LABEL: extract_v8float_halves:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: str q1, [x1]
+; CHECK-NEXT: str q0, [x2]
+; CHECK-NEXT: ret
+entry:
+ %b = load <8 x float>, ptr %in
+ %hi = shufflevector <8 x float> %b, <8 x float> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ store <4 x float> %hi, ptr %out
+ %lo = shufflevector <8 x float> %b, <8 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ store <4 x float> %lo, ptr %out2
+ ret void
+}
+
define void @extract_subvector_v16f32(ptr %a, ptr %b) #0 {
; CHECK-LABEL: extract_subvector_v16f32:
; CHECK: // %bb.0:
@@ -444,6 +696,25 @@ define void @extract_subvector_v16f32(ptr %a, ptr %b) #0 {
ret void
}
+define void @extract_v16float_halves(ptr %in, ptr %out, ptr %out2) #0 vscale_range(4,4) {
+; CHECK-LABEL: extract_v16float_halves:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: ptrue p0.s, vl8
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #32
+; CHECK-NEXT: st1w { z1.s }, p0, [x1]
+; CHECK-NEXT: st1w { z0.s }, p0, [x2]
+; CHECK-NEXT: ret
+entry:
+ %b = load <16 x float>, ptr %in
+ %hi = shufflevector <16 x float> %b, <16 x float> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ store <8 x float> %hi, ptr %out
+ %lo = shufflevector <16 x float> %b, <16 x float> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ store <8 x float> %lo, ptr %out2
+ ret void
+}
+
define void @extract_subvector_v32f32(ptr %a, ptr %b) vscale_range(8,0) #0 {
; CHECK-LABEL: extract_subvector_v32f32:
; CHECK: // %bb.0:
@@ -497,6 +768,24 @@ define void @extract_subvector_v4f64(ptr %a, ptr %b) vscale_range(2,0) #0 {
ret void
}
+define void @extract_v4double_halves(ptr %in, ptr %out, ptr %out2) #0 vscale_range(2,2) {
+; CHECK-LABEL: extract_v4double_halves:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
+; CHECK-NEXT: str q1, [x1]
+; CHECK-NEXT: str q0, [x2]
+; CHECK-NEXT: ret
+entry:
+ %b = load <4 x double>, ptr %in
+ %hi = shufflevector <4 x double> %b, <4 x double> poison, <2 x i32> <i32 2, i32 3>
+ store <2 x double> %hi, ptr %out
+ %lo = shufflevector <4 x double> %b, <4 x double> poison, <2 x i32> <i32 0, i32 1>
+ store <2 x double> %lo, ptr %out2
+ ret void
+}
+
define void @extract_subvector_v8f64(ptr %a, ptr %b) #0 {
; CHECK-LABEL: extract_subvector_v8f64:
; CHECK: // %bb.0:
@@ -511,6 +800,25 @@ define void @extract_subvector_v8f64(ptr %a, ptr %b) #0 {
ret void
}
+define void @extract_v8double_halves(ptr %in, ptr %out, ptr %out2) #0 vscale_range(4,4) {
+; CHECK-LABEL: extract_v8double_halves:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: ptrue p0.d, vl4
+; CHECK-NEXT: mov z1.d, z0.d
+; CHECK-NEXT: ext z1.b, z1.b, z0.b, #32
+; CHECK-NEXT: st1d { z1.d }, p0, [x1]
+; CHECK-NEXT: st1d { z0.d }, p0, [x2]
+; CHECK-NEXT: ret
+entry:
+ %b = load <8 x double>, ptr %in
+ %hi = shufflevector <8 x double> %b, <8 x double> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ store <4 x double> %hi, ptr %out
+ %lo = shufflevector <8 x double> %b, <8 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ store <4 x double> %lo, ptr %out2
+ ret void
+}
+
define void @extract_subvector_v16f64(ptr %a, ptr %b) vscale_range(8,0) #0 {
; CHECK-LABEL: extract_subvector_v16f64:
; CHECK: // %bb.0:
@@ -539,13 +847,65 @@ define void @extract_subvector_v32f64(ptr %a, ptr %b) vscale_range(16,0) #0 {
ret void
}
+; bf16
+
+define void @extract_v8bfloat_halves(ptr %in, ptr %out, ptr %out2) #0 {
+; CHECK-LABEL: extract_v8bfloat_halves:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: str d1, [x1]
+; CHECK-NEXT: str d0, [x2]
+; CHECK-NEXT: ret
+entry:
+ %b = load <8 x bfloat>, ptr %in
+ %hi = shufflevector <8 x bfloat> %b, <8 x bfloat> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ store <4 x bfloat> %hi, ptr %out
+ %lo = shufflevector <8 x bfloat> %b, <8 x bfloat> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ store <4 x bfloat> %lo, ptr %out2
+ ret void
+}
+
+define void @extract_v16bfloat_halves(ptr %in, ptr %out, ptr %out2) #0 vscale_range(2,2) {
+; CHECK-LABEL: extract_v16bfloat_halves:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldp q1, q0, [x0]
+; CHECK-NEXT: str q0, [x1]
+; CHECK-NEXT: str q1, [x2]
+; CHECK-NEXT: ret
+entry:
+ %b = load <16 x bfloat>, ptr %in
+ %hi = shufflevector <16 x bfloat> %b, <16 x bfloat> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ store <8 x bfloat> %hi, ptr %out
+ %lo = shufflevector <16 x bfloat> %b, <16 x bfloat> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ store <8 x bfloat> %lo, ptr %out2
+ ret void
+}
+
+define void @extract_v32bfloat_halves(ptr %in, ptr %out, ptr %out2) #0 vscale_range(4,4) {
+; CHECK-LABEL: extract_v32bfloat_halves:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldp q0, q1, [x0, #32]
+; CHECK-NEXT: ldp q3, q2, [x0]
+; CHECK-NEXT: stp q0, q1, [x1]
+; CHECK-NEXT: stp q3, q2, [x2]
+; CHECK-NEXT: ret
+entry:
+ %b = load <32 x bfloat>, ptr %in
+ %hi = shufflevector <32 x bfloat> %b, <32 x bfloat> poison, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+ store <16 x bfloat> %hi, ptr %out
+ %lo = shufflevector <32 x bfloat> %b, <32 x bfloat> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ store <16 x bfloat> %lo, ptr %out2
+ ret void
+}
+
; Test for infinite loop due to fold:
; extract_subvector(insert_subvector(x,y,c1),c2)--> extract_subvector(y,c2-c1)
define void @extract_subvector_legalization_v8i32() vscale_range(2,2) #0 {
; CHECK-LABEL: extract_subvector_legalization_v8i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: adrp x8, .LCPI40_0
-; CHECK-NEXT: add x8, x8, :lo12:.LCPI40_0
+; CHECK-NEXT: adrp x8, .LCPI59_0
+; CHECK-NEXT: add x8, x8, :lo12:.LCPI59_0
; CHECK-NEXT: ptrue p1.d
; CHECK-NEXT: ldr z0, [x8]
; CHECK-NEXT: mov z1.d, z0.d
@@ -556,11 +916,11 @@ define void @extract_subvector_legalization_v8i32() vscale_range(2,2) #0 {
; CHECK-NEXT: sunpklo z1.d, z1.s
; CHECK-NEXT: cmpne p0.d, p1/z, z1.d, #0
; CHECK-NEXT: cmpne p1.d, p1/z, z0.d, #0
-; CHECK-NEXT: .LBB40_1: // %body
+; CHECK-NEXT: .LBB59_1: // %body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: st1d { z0.d }, p1, [x8]
; CHECK-NEXT: st1d { z0.d }, p0, [x8]
-; CHECK-NEXT: b .LBB40_1
+; CHECK-NEXT: b .LBB59_1
entry:
%splat = shufflevector <8 x i32> poison, <8 x i32> poison, <8 x i32> zeroinitializer
br label %body
diff --git a/llvm/test/CodeGen/AArch64/sve-vector-splice.ll b/llvm/test/CodeGen/AArch64/sve-vector-splice.ll
new file mode 100644
index 0000000000000..33c2ce68b0aac
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-vector-splice.ll
@@ -0,0 +1,162 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mattr=+sve -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mattr=+sve2 -verify-machineinstrs < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+; Test vector_splice patterns.
+; Note that this test is similar to named-vector-shuffles-sve.ll, but it focuses
+; on testing all supported types, and a positive "splice index".
+
+
+; i8 elements
+define <vscale x 16 x i8> @splice_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: splice_nxv16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext z0.b, z0.b, z1.b, #1
+; CHECK-NEXT: ret
+ %res = call <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 1)
+ ret <vscale x 16 x i8> %res
+}
+
+; i16 elements
+define <vscale x 8 x i16> @splice_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
+; CHECK-LABEL: splice_nxv8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext z0.b, z0.b, z1.b, #2
+; CHECK-NEXT: ret
+ %res = call <vscale x 8 x i16> @llvm.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 1)
+ ret <vscale x 8 x i16> %res
+}
+
+; bf16 elements
+
+define <vscale x 8 x bfloat> @splice_nxv8bfloat(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
+; CHECK-LABEL: splice_nxv8bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext z0.b, z0.b, z1.b, #2
+; CHECK-NEXT: ret
+ %res = call <vscale x 8 x bfloat> @llvm.vector.splice.nxv8bfloat(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, i32 1)
+ ret <vscale x 8 x bfloat> %res
+}
+
+define <vscale x 4 x bfloat> @splice_nxv4bfloat(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) {
+; CHECK-LABEL: splice_nxv4bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext z0.b, z0.b, z1.b, #4
+; CHECK-NEXT: ret
+ %res = call <vscale x 4 x bfloat> @llvm.vector.splice.nxv4bfloat(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b, i32 1)
+ ret <vscale x 4 x bfloat> %res
+}
+
+define <vscale x 2 x bfloat> @splice_nxv2bfloat(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) {
+; CHECK-LABEL: splice_nxv2bfloat:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8
+; CHECK-NEXT: ret
+ %res = call <vscale x 2 x bfloat> @llvm.vector.splice.nxv4bfloat(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b, i32 1)
+ ret <vscale x 2 x bfloat> %res
+}
+
+; f16 elements
+
+define <vscale x 8 x half> @splice_nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) {
+; CHECK-LABEL: splice_nxv8f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext z0.b, z0.b, z1.b, #2
+; CHECK-NEXT: ret
+ %res = call <vscale x 8 x half> @llvm.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 1)
+ ret <vscale x 8 x half> %res
+}
+
+define <vscale x 4 x half> @splice_nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b) {
+; CHECK-LABEL: splice_nxv4f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext z0.b, z0.b, z1.b, #4
+; CHECK-NEXT: ret
+ %res = call <vscale x 4 x half> @llvm.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 1)
+ ret <vscale x 4 x half> %res
+}
+
+define <vscale x 2 x half> @splice_nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b) {
+; CHECK-LABEL: splice_nxv2f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8
+; CHECK-NEXT: ret
+ %res = call <vscale x 2 x half> @llvm.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 1)
+ ret <vscale x 2 x half> %res
+}
+
+; i32 elements
+define <vscale x 4 x i32> @splice_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: splice_nxv4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext z0.b, z0.b, z1.b, #4
+; CHECK-NEXT: ret
+ %res = call <vscale x 4 x i32> @llvm.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 1)
+ ret <vscale x 4 x i32> %res
+}
+
+; f32 elements
+
+define <vscale x 4 x float> @splice_nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {
+; CHECK-LABEL: splice_nxv4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext z0.b, z0.b, z1.b, #4
+; CHECK-NEXT: ret
+ %res = call <vscale x 4 x float> @llvm.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 1)
+ ret <vscale x 4 x float> %res
+}
+
+define <vscale x 2 x float> @splice_nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b) {
+; CHECK-LABEL: splice_nxv2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8
+; CHECK-NEXT: ret
+ %res = call <vscale x 2 x float> @llvm.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 1)
+ ret <vscale x 2 x float> %res
+}
+
+; i64 elements
+define <vscale x 2 x i64> @splice_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: splice_nxv2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8
+; CHECK-NEXT: ret
+ %res = call <vscale x 2 x i64> @llvm.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 1)
+ ret <vscale x 2 x i64> %res
+}
+
+; f64 elements
+define <vscale x 2 x double> @splice_nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {
+; CHECK-LABEL: splice_nxv2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8
+; CHECK-NEXT: ret
+ %res = call <vscale x 2 x double> @llvm.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 1)
+ ret <vscale x 2 x double> %res
+}
+
+declare <vscale x 2 x i1> @llvm.vector.splice.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, i32)
+declare <vscale x 4 x i1> @llvm.vector.splice.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>, i32)
+declare <vscale x 8 x i1> @llvm.vector.splice.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>, i32)
+declare <vscale x 16 x i1> @llvm.vector.splice.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, i32)
+
+declare <vscale x 2 x i8> @llvm.vector.splice.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>, i32)
+declare <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32)
+declare <vscale x 8 x i16> @llvm.vector.splice.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)
+declare <vscale x 4 x i32> @llvm.vector.splice.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)
+declare <vscale x 8 x i32> @llvm.vector.splice.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>, i32)
+declare <vscale x 2 x i64> @llvm.vector.splice.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32)
+
+declare <vscale x 2 x half> @llvm.vector.splice.nxv2f16(<vscale x 2 x half>, <vscale x 2 x half>, i32)
+declare <vscale x 4 x half> @llvm.vector.splice.nxv4f16(<vscale x 4 x half>, <vscale x 4 x half>, i32)
+declare <vscale x 8 x half> @llvm.vector.splice.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32)
+declare <vscale x 2 x float> @llvm.vector.splice.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>, i32)
+declare <vscale x 4 x float> @llvm.vector.splice.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, i32)
+declare <vscale x 16 x float> @llvm.vector.splice.nxv16f32(<vscale x 16 x float>, <vscale x 16 x float>, i32)
+declare <vscale x 2 x double> @llvm.vector.splice.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, i32)
+
+declare <vscale x 2 x bfloat> @llvm.vector.splice.nxv2bf16(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i32)
+declare <vscale x 4 x bfloat> @llvm.vector.splice.nxv4bf16(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i32)
+declare <vscale x 8 x bfloat> @llvm.vector.splice.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32)
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