[llvm-branch-commits] [llvm] [AArch64][ISel] Select constructive SVE2 ext instruction (PR #151730)

[Sander de Smalen via llvm-branch-commits]

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@@ -4069,6 +4069,22 @@ let Predicates = [HasSVE2_or_SME] in {
   let AddedComplexity = 2 in {
     def : Pat<(nxv16i8 (AArch64ext nxv16i8:$zn1, nxv16i8:$zn2, (i32 imm0_255:$imm))),
               (EXT_ZZI_B (REG_SEQUENCE ZPR2, $zn1, zsub0, $zn2, zsub1), imm0_255:$imm)>;
+
+    foreach VT = [nxv16i8] in
+      def : Pat<(VT (vector_splice VT:$Z1, VT:$Z2, (i64 (sve_ext_imm_0_255 i32:$index)))),
+                (EXT_ZZI_B  (REG_SEQUENCE ZPR2, $Z1, zsub0, $Z2, zsub1), imm0_255:$index)>;
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sdesmalen-arm wrote:

> What do you mean by different output? Do you mean that if you replce the splice intrisics with AArch64's EXT intrinsics, then llvm/test/CodeGen/AArch64/sve-vector-splice.ll has different CHECK lines?

What I meant was that if the output would be the same, you probably wouldn't have added this pattern. So I'm basically asking "why wouldn't the above pattern already cover this?".

> When you say removing the former, do you mean removing the pattern?

I mean removing `AArch64ISD::EXT` in favour of `ISD::VECTOR_SPLICE`. The EXT and SPLICE _SVE instructions_ are indeed different (the former takes an immediate, the latter a predicate), but I think the `AArch64ISD::EXT` and `ISD::VECTOR_SPLICE` _SelectionDAG nodes_ are practically the same. Before SVE we didn't have to create a new ISD node for this because `ISD::VECTOR_SHUFFLE` described this pattern sufficiently, but that couldn't be used for scalable vectors and so we added the generic `ISD::VECTOR_SPLICE`. At the time there probably wasn't an incentive to replace uses of `AArch64ISD::EXT` by `ISD::VECTOR_SPLICE`, but if code-gen is different depending on which node we try to match, then I think there's an incentive to merge the two.

https://github.com/llvm/llvm-project/pull/151730