[llvm-branch-commits] [llvm] [AArch64][ISel] Select constructive SVE2 ext instruction (PR #151730)

[Gaëtan Bossu via llvm-branch-commits]

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@@ -109,14 +109,13 @@ define <16 x i16> @two_way_i8_i16_vl256(ptr %accptr, ptr %uptr, ptr %sptr) vscal
 ; SME-LABEL: two_way_i8_i16_vl256:
 ; SME:       // %bb.0:
 ; SME-NEXT:    ldr z0, [x0]
-; SME-NEXT:    ldr z1, [x1]
-; SME-NEXT:    ldr z2, [x2]
-; SME-NEXT:    umlalb z0.h, z2.b, z1.b
-; SME-NEXT:    umlalt z0.h, z2.b, z1.b
-; SME-NEXT:    mov z1.d, z0.d
-; SME-NEXT:    ext z1.b, z1.b, z0.b, #16
-; SME-NEXT:    // kill: def $q0 killed $q0 killed $z0
-; SME-NEXT:    // kill: def $q1 killed $q1 killed $z1
+; SME-NEXT:    ldr z2, [x1]
+; SME-NEXT:    ldr z3, [x2]
+; SME-NEXT:    umlalb z0.h, z3.b, z2.b
+; SME-NEXT:    umlalt z0.h, z3.b, z2.b
+; SME-NEXT:    ext z2.b, { z0.b, z1.b }, #16
+; SME-NEXT:    // kill: def $q0 killed $q0 killed $z0_z1
+; SME-NEXT:    mov z1.d, z2.d
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gbossu wrote:

This is one example where we would gain by having subreg liveness.

Currently the `ret` instruction has an implicit use of `z0` and `z1` for ABI reasons. This forces a use of all aliasing registers, including `z0_z1`, which will be considered live from `umlalt z0.h, z3.b, z2.b`. As a consequence, `ext z2.b, { z0.b, z1.b }, #16` cannot be rewritten directly as `ext z1.b, { z0.b, z1.b }, #16` as it would create an interference. With subreg liveness enabled, we would see there is no interference for `z0_z1.hi`.

https://github.com/llvm/llvm-project/pull/151730