[llvm-branch-commits] [SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3 (PR #135714)

[via llvm-branch-commits]

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@@ -294,4 +294,13 @@ def : Pat<(f32 fpnegimm0), (FNEGS (FZEROS))>;
 // VIS3 instruction patterns.
 let Predicates = [HasVIS3] in {
 def : Pat<(i64 (adde i64:$lhs, i64:$rhs)), (ADDXCCC $lhs, $rhs)>;
+
+def : Pat<(i64 (mulhu i64:$lhs, i64:$rhs)), (UMULXHI $lhs, $rhs)>;
+// Signed "MULXHI".
+// Based on the formula presented in OSA2011 §7.140, but with bitops to select
+// the values to be added.
+def : Pat<(i64 (mulhs i64:$lhs, i64:$rhs)),
+      (SUBrr (UMULXHI $lhs, $rhs),
+             (ADDrr (ANDrr (SRAXri $lhs, 63), $rhs),
+                    (ANDrr (SRAXri $rhs, 63), $lhs)))>;
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koachan wrote:

It works, in that it cuts down on the number of multiplies, but it still seems to produce more instructions than manual matching (e.g in `signed_multiply_extend`):
```
; VIS3-LABEL: signed_multiply_extend:
; VIS3:       ! %bb.0:
; VIS3-NEXT:    srax %o0, 63, %o2
; VIS3-NEXT:    srax %o1, 63, %o3
; VIS3-NEXT:    umulxhi %o1, %o0, %o4
; VIS3-NEXT:    sub %g0, %o1, %o5
; VIS3-NEXT:    and %o2, %o5, %o2
; VIS3-NEXT:    add %o4, %o2, %o2
; VIS3-NEXT:    sub %g0, %o0, %o4
; VIS3-NEXT:    and %o3, %o4, %o3
; VIS3-NEXT:    add %o2, %o3, %o2
; VIS3-NEXT:    mulx %o1, %o0, %o1
; VIS3-NEXT:    retl
; VIS3-NEXT:    mov %o2, %o0
```

https://github.com/llvm/llvm-project/pull/135714