[llvm-branch-commits] [RISCV][NFC] Use bitmasks generated by TableGen (PR #135600)
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Mon Apr 14 01:56:20 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Pengcheng Wang (wangpc-pp)
<details>
<summary>Changes</summary>
So that we don't need to sync-up the table manually.
---
Full diff: https://github.com/llvm/llvm-project/pull/135600.diff
3 Files Affected:
- (modified) llvm/include/llvm/TargetParser/RISCVTargetParser.h (-8)
- (modified) llvm/lib/TargetParser/RISCVISAInfo.cpp (+11-31)
- (modified) llvm/lib/TargetParser/RISCVTargetParser.cpp (-15)
``````````diff
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index 6e231d32e7897..e0105685c210d 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -24,14 +24,6 @@ class Triple;
namespace RISCV {
-namespace RISCVExtensionBitmaskTable {
-struct RISCVExtensionBitmask {
- const char *Name;
- unsigned GroupID;
- unsigned BitPosition;
-};
-} // namespace RISCVExtensionBitmaskTable
-
struct CPUModel {
uint32_t MVendorID;
uint64_t MArchID;
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 4ff2fb11b1b00..524d6dc01e8aa 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -1048,41 +1048,21 @@ struct RISCVExtBit {
uint8_t bitpos;
};
-constexpr static RISCVExtBit RISCVBitPositions[] = {
- {"a", 0, 0}, {"c", 0, 2},
- {"d", 0, 3}, {"f", 0, 5},
- {"i", 0, 8}, {"m", 0, 12},
- {"v", 0, 21}, {"zacas", 0, 26},
- {"zba", 0, 27}, {"zbb", 0, 28},
- {"zbc", 0, 29}, {"zbkb", 0, 30},
- {"zbkc", 0, 31}, {"zbkx", 0, 32},
- {"zbs", 0, 33}, {"zfa", 0, 34},
- {"zfh", 0, 35}, {"zfhmin", 0, 36},
- {"zicboz", 0, 37}, {"zicond", 0, 38},
- {"zihintntl", 0, 39}, {"zihintpause", 0, 40},
- {"zknd", 0, 41}, {"zkne", 0, 42},
- {"zknh", 0, 43}, {"zksed", 0, 44},
- {"zksh", 0, 45}, {"zkt", 0, 46},
- {"ztso", 0, 47}, {"zvbb", 0, 48},
- {"zvbc", 0, 49}, {"zvfh", 0, 50},
- {"zvfhmin", 0, 51}, {"zvkb", 0, 52},
- {"zvkg", 0, 53}, {"zvkned", 0, 54},
- {"zvknha", 0, 55}, {"zvknhb", 0, 56},
- {"zvksed", 0, 57}, {"zvksh", 0, 58},
- {"zvkt", 0, 59}, {"zve32x", 0, 60},
- {"zve32f", 0, 61}, {"zve64x", 0, 62},
- {"zve64f", 0, 63}, {"zve64d", 1, 0},
- {"zimop", 1, 1}, {"zca", 1, 2},
- {"zcb", 1, 3}, {"zcd", 1, 4},
- {"zcf", 1, 5}, {"zcmop", 1, 6},
- {"zawrs", 1, 7}};
+struct RISCVExtensionBitmask {
+ const char *Name;
+ unsigned GroupID;
+ unsigned BitPosition;
+};
+
+#define GET_RISCVExtensionBitmaskTable_IMPL
+#include "llvm/TargetParser/RISCVTargetParserDef.inc"
std::pair<int, int> RISCVISAInfo::getRISCVFeaturesBitsInfo(StringRef Ext) {
// Note that this code currently accepts mixed case extension names, but
// does not handle extension versions at all. That's probably fine because
// there's only one extension version in the __riscv_feature_bits vector.
- for (auto E : RISCVBitPositions)
- if (E.ext.equals_insensitive(Ext))
- return std::make_pair(E.groupid, E.bitpos);
+ for (auto E : ExtensionBitmask)
+ if (Ext.equals_insensitive(E.Name))
+ return std::make_pair(E.GroupID, E.BitPosition);
return std::make_pair(-1, -1);
}
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 4111f8bfd2662..5bd7de1d3ca46 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -138,21 +138,6 @@ void getFeaturesForCPU(StringRef CPU,
EnabledFeatures.push_back(F.substr(1));
}
-namespace RISCVExtensionBitmaskTable {
-#define GET_RISCVExtensionBitmaskTable_IMPL
-#include "llvm/TargetParser/RISCVTargetParserDef.inc"
-
-} // namespace RISCVExtensionBitmaskTable
-
-namespace {
-struct LessExtName {
- bool operator()(const RISCVExtensionBitmaskTable::RISCVExtensionBitmask &LHS,
- StringRef RHS) {
- return StringRef(LHS.Name) < RHS;
- }
-};
-} // namespace
-
} // namespace RISCV
namespace RISCVVType {
``````````
</details>
https://github.com/llvm/llvm-project/pull/135600
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