[llvm-branch-commits] [clang] Backport "[Clang][CodeGen] Fix type for atomic float incdec operators (#107075)" (PR #107184)
Yingwei Zheng via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Sep 3 22:51:25 PDT 2024
https://github.com/dtcxzyw created https://github.com/llvm/llvm-project/pull/107184
Backport 9fef09fd2918e7d8c357b98a9a798fe207941f73.
>From b247a5774de77002b48257e2ce885b7ae34e9faf Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Wed, 4 Sep 2024 12:19:46 +0800
Subject: [PATCH] [Clang][CodeGen] Fix type for atomic float incdec operators
(#107075)
`llvm::ConstantFP::get(llvm::LLVMContext&, APFloat(float))` always
returns a f32 constant.
Fix https://github.com/llvm/llvm-project/issues/107054.
---
clang/lib/CodeGen/CGExprScalar.cpp | 26 +-
clang/test/CodeGen/X86/x86-atomic-double.c | 88 +++---
.../test/CodeGen/X86/x86-atomic-long_double.c | 293 ++++++++++++++----
3 files changed, 300 insertions(+), 107 deletions(-)
diff --git a/clang/lib/CodeGen/CGExprScalar.cpp b/clang/lib/CodeGen/CGExprScalar.cpp
index a17d68424bbce5..6e212e74676e8d 100644
--- a/clang/lib/CodeGen/CGExprScalar.cpp
+++ b/clang/lib/CodeGen/CGExprScalar.cpp
@@ -2833,18 +2833,22 @@ ScalarExprEmitter::EmitScalarPrePostIncDec(const UnaryOperator *E, LValue LV,
llvm::AtomicOrdering::SequentiallyConsistent);
return isPre ? Builder.CreateBinOp(op, old, amt) : old;
}
- // Special case for atomic increment/decrement on floats
+ // Special case for atomic increment/decrement on floats.
+ // Bail out non-power-of-2-sized floating point types (e.g., x86_fp80).
if (type->isFloatingType()) {
- llvm::AtomicRMWInst::BinOp aop =
- isInc ? llvm::AtomicRMWInst::FAdd : llvm::AtomicRMWInst::FSub;
- llvm::Instruction::BinaryOps op =
- isInc ? llvm::Instruction::FAdd : llvm::Instruction::FSub;
- llvm::Value *amt = llvm::ConstantFP::get(
- VMContext, llvm::APFloat(static_cast<float>(1.0)));
- llvm::Value *old =
- Builder.CreateAtomicRMW(aop, LV.getAddress(), amt,
- llvm::AtomicOrdering::SequentiallyConsistent);
- return isPre ? Builder.CreateBinOp(op, old, amt) : old;
+ llvm::Type *Ty = ConvertType(type);
+ if (llvm::has_single_bit(Ty->getScalarSizeInBits())) {
+ llvm::AtomicRMWInst::BinOp aop =
+ isInc ? llvm::AtomicRMWInst::FAdd : llvm::AtomicRMWInst::FSub;
+ llvm::Instruction::BinaryOps op =
+ isInc ? llvm::Instruction::FAdd : llvm::Instruction::FSub;
+ llvm::Value *amt = llvm::ConstantFP::get(Ty, 1.0);
+ llvm::AtomicRMWInst *old = Builder.CreateAtomicRMW(
+ aop, LV.getAddress(), amt,
+ llvm::AtomicOrdering::SequentiallyConsistent);
+
+ return isPre ? Builder.CreateBinOp(op, old, amt) : old;
+ }
}
value = EmitLoadOfLValue(LV, E->getExprLoc());
input = value;
diff --git a/clang/test/CodeGen/X86/x86-atomic-double.c b/clang/test/CodeGen/X86/x86-atomic-double.c
index 2354c89cc2b170..09c8f70c3db854 100644
--- a/clang/test/CodeGen/X86/x86-atomic-double.c
+++ b/clang/test/CodeGen/X86/x86-atomic-double.c
@@ -6,20 +6,14 @@
// X64-LABEL: define dso_local double @test_double_post_inc(
// X64-SAME: ) #[[ATTR0:[0-9]+]] {
// X64-NEXT: entry:
-// X64-NEXT: [[RETVAL:%.*]] = alloca double, align 8
-// X64-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr @test_double_post_inc.n, float 1.000000e+00 seq_cst, align 8
-// X64-NEXT: store float [[TMP0]], ptr [[RETVAL]], align 8
-// X64-NEXT: [[TMP1:%.*]] = load double, ptr [[RETVAL]], align 8
-// X64-NEXT: ret double [[TMP1]]
+// X64-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr @test_double_post_inc.n, double 1.000000e+00 seq_cst, align 8
+// X64-NEXT: ret double [[TMP0]]
//
// X86-LABEL: define dso_local double @test_double_post_inc(
// X86-SAME: ) #[[ATTR0:[0-9]+]] {
// X86-NEXT: entry:
-// X86-NEXT: [[RETVAL:%.*]] = alloca double, align 4
-// X86-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr @test_double_post_inc.n, float 1.000000e+00 seq_cst, align 8
-// X86-NEXT: store float [[TMP0]], ptr [[RETVAL]], align 4
-// X86-NEXT: [[TMP1:%.*]] = load double, ptr [[RETVAL]], align 4
-// X86-NEXT: ret double [[TMP1]]
+// X86-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr @test_double_post_inc.n, double 1.000000e+00 seq_cst, align 8
+// X86-NEXT: ret double [[TMP0]]
//
double test_double_post_inc()
{
@@ -30,20 +24,14 @@ double test_double_post_inc()
// X64-LABEL: define dso_local double @test_double_post_dc(
// X64-SAME: ) #[[ATTR0]] {
// X64-NEXT: entry:
-// X64-NEXT: [[RETVAL:%.*]] = alloca double, align 8
-// X64-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr @test_double_post_dc.n, float 1.000000e+00 seq_cst, align 8
-// X64-NEXT: store float [[TMP0]], ptr [[RETVAL]], align 8
-// X64-NEXT: [[TMP1:%.*]] = load double, ptr [[RETVAL]], align 8
-// X64-NEXT: ret double [[TMP1]]
+// X64-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr @test_double_post_dc.n, double 1.000000e+00 seq_cst, align 8
+// X64-NEXT: ret double [[TMP0]]
//
// X86-LABEL: define dso_local double @test_double_post_dc(
// X86-SAME: ) #[[ATTR0]] {
// X86-NEXT: entry:
-// X86-NEXT: [[RETVAL:%.*]] = alloca double, align 4
-// X86-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr @test_double_post_dc.n, float 1.000000e+00 seq_cst, align 8
-// X86-NEXT: store float [[TMP0]], ptr [[RETVAL]], align 4
-// X86-NEXT: [[TMP1:%.*]] = load double, ptr [[RETVAL]], align 4
-// X86-NEXT: ret double [[TMP1]]
+// X86-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr @test_double_post_dc.n, double 1.000000e+00 seq_cst, align 8
+// X86-NEXT: ret double [[TMP0]]
//
double test_double_post_dc()
{
@@ -54,22 +42,16 @@ double test_double_post_dc()
// X64-LABEL: define dso_local double @test_double_pre_dc(
// X64-SAME: ) #[[ATTR0]] {
// X64-NEXT: entry:
-// X64-NEXT: [[RETVAL:%.*]] = alloca double, align 8
-// X64-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr @test_double_pre_dc.n, float 1.000000e+00 seq_cst, align 8
-// X64-NEXT: [[TMP1:%.*]] = fsub float [[TMP0]], 1.000000e+00
-// X64-NEXT: store float [[TMP1]], ptr [[RETVAL]], align 8
-// X64-NEXT: [[TMP2:%.*]] = load double, ptr [[RETVAL]], align 8
-// X64-NEXT: ret double [[TMP2]]
+// X64-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr @test_double_pre_dc.n, double 1.000000e+00 seq_cst, align 8
+// X64-NEXT: [[TMP1:%.*]] = fsub double [[TMP0]], 1.000000e+00
+// X64-NEXT: ret double [[TMP1]]
//
// X86-LABEL: define dso_local double @test_double_pre_dc(
// X86-SAME: ) #[[ATTR0]] {
// X86-NEXT: entry:
-// X86-NEXT: [[RETVAL:%.*]] = alloca double, align 4
-// X86-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr @test_double_pre_dc.n, float 1.000000e+00 seq_cst, align 8
-// X86-NEXT: [[TMP1:%.*]] = fsub float [[TMP0]], 1.000000e+00
-// X86-NEXT: store float [[TMP1]], ptr [[RETVAL]], align 4
-// X86-NEXT: [[TMP2:%.*]] = load double, ptr [[RETVAL]], align 4
-// X86-NEXT: ret double [[TMP2]]
+// X86-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr @test_double_pre_dc.n, double 1.000000e+00 seq_cst, align 8
+// X86-NEXT: [[TMP1:%.*]] = fsub double [[TMP0]], 1.000000e+00
+// X86-NEXT: ret double [[TMP1]]
//
double test_double_pre_dc()
{
@@ -80,25 +62,43 @@ double test_double_pre_dc()
// X64-LABEL: define dso_local double @test_double_pre_inc(
// X64-SAME: ) #[[ATTR0]] {
// X64-NEXT: entry:
-// X64-NEXT: [[RETVAL:%.*]] = alloca double, align 8
-// X64-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr @test_double_pre_inc.n, float 1.000000e+00 seq_cst, align 8
-// X64-NEXT: [[TMP1:%.*]] = fadd float [[TMP0]], 1.000000e+00
-// X64-NEXT: store float [[TMP1]], ptr [[RETVAL]], align 8
-// X64-NEXT: [[TMP2:%.*]] = load double, ptr [[RETVAL]], align 8
-// X64-NEXT: ret double [[TMP2]]
+// X64-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr @test_double_pre_inc.n, double 1.000000e+00 seq_cst, align 8
+// X64-NEXT: [[TMP1:%.*]] = fadd double [[TMP0]], 1.000000e+00
+// X64-NEXT: ret double [[TMP1]]
//
// X86-LABEL: define dso_local double @test_double_pre_inc(
// X86-SAME: ) #[[ATTR0]] {
// X86-NEXT: entry:
-// X86-NEXT: [[RETVAL:%.*]] = alloca double, align 4
-// X86-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr @test_double_pre_inc.n, float 1.000000e+00 seq_cst, align 8
-// X86-NEXT: [[TMP1:%.*]] = fadd float [[TMP0]], 1.000000e+00
-// X86-NEXT: store float [[TMP1]], ptr [[RETVAL]], align 4
-// X86-NEXT: [[TMP2:%.*]] = load double, ptr [[RETVAL]], align 4
-// X86-NEXT: ret double [[TMP2]]
+// X86-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr @test_double_pre_inc.n, double 1.000000e+00 seq_cst, align 8
+// X86-NEXT: [[TMP1:%.*]] = fadd double [[TMP0]], 1.000000e+00
+// X86-NEXT: ret double [[TMP1]]
//
double test_double_pre_inc()
{
static _Atomic double n;
return ++n;
}
+
+// X64-LABEL: define dso_local i32 @pr107054(
+// X64-SAME: ) #[[ATTR0]] {
+// X64-NEXT: entry:
+// X64-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr @pr107054.n, double 1.000000e+00 seq_cst, align 8
+// X64-NEXT: [[TMP1:%.*]] = fadd double [[TMP0]], 1.000000e+00
+// X64-NEXT: [[CMP:%.*]] = fcmp oeq double [[TMP1]], 1.000000e+00
+// X64-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i32
+// X64-NEXT: ret i32 [[CONV]]
+//
+// X86-LABEL: define dso_local i32 @pr107054(
+// X86-SAME: ) #[[ATTR0]] {
+// X86-NEXT: entry:
+// X86-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr @pr107054.n, double 1.000000e+00 seq_cst, align 8
+// X86-NEXT: [[TMP1:%.*]] = fadd double [[TMP0]], 1.000000e+00
+// X86-NEXT: [[CMP:%.*]] = fcmp oeq double [[TMP1]], 1.000000e+00
+// X86-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i32
+// X86-NEXT: ret i32 [[CONV]]
+//
+int pr107054()
+{
+ static _Atomic double n;
+ return (++n) == 1;
+}
diff --git a/clang/test/CodeGen/X86/x86-atomic-long_double.c b/clang/test/CodeGen/X86/x86-atomic-long_double.c
index 2c3f381f13511e..9c82784807daca 100644
--- a/clang/test/CodeGen/X86/x86-atomic-long_double.c
+++ b/clang/test/CodeGen/X86/x86-atomic-long_double.c
@@ -4,29 +4,60 @@
// X64-LABEL: define dso_local x86_fp80 @testinc(
// X64-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0:[0-9]+]] {
-// X64-NEXT: [[ENTRY:.*:]]
-// X64-NEXT: [[RETVAL:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ENTRY:.*]]:
// X64-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 8
+// X64-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca x86_fp80, align 16
// X64-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 8
// X64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 8
-// X64-NEXT: [[TMP1:%.*]] = atomicrmw fadd ptr [[TMP0]], float 1.000000e+00 seq_cst, align 16
-// X64-NEXT: [[TMP2:%.*]] = fadd float [[TMP1]], 1.000000e+00
-// X64-NEXT: store float [[TMP2]], ptr [[RETVAL]], align 16
-// X64-NEXT: [[TMP3:%.*]] = load x86_fp80, ptr [[RETVAL]], align 16
-// X64-NEXT: ret x86_fp80 [[TMP3]]
+// X64-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i128, ptr [[TMP0]] seq_cst, align 16
+// X64-NEXT: store i128 [[ATOMIC_LOAD]], ptr [[ATOMIC_TEMP]], align 16
+// X64-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 16
+// X64-NEXT: br label %[[ATOMIC_OP:.*]]
+// X64: [[ATOMIC_OP]]:
+// X64-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP8:%.*]], %[[ATOMIC_OP]] ]
+// X64-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP2]], 0xK3FFF8000000000000000
+// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)
+// X64-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 16
+// X64-NEXT: [[TMP3:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 16
+// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP2]], i8 0, i64 16, i1 false)
+// X64-NEXT: store x86_fp80 [[INC]], ptr [[ATOMIC_TEMP2]], align 16
+// X64-NEXT: [[TMP4:%.*]] = load i128, ptr [[ATOMIC_TEMP2]], align 16
+// X64-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[TMP0]], i128 [[TMP3]], i128 [[TMP4]] seq_cst seq_cst, align 16
+// X64-NEXT: [[TMP6:%.*]] = extractvalue { i128, i1 } [[TMP5]], 0
+// X64-NEXT: [[TMP7:%.*]] = extractvalue { i128, i1 } [[TMP5]], 1
+// X64-NEXT: store i128 [[TMP6]], ptr [[ATOMIC_TEMP3]], align 16
+// X64-NEXT: [[TMP8]] = load x86_fp80, ptr [[ATOMIC_TEMP3]], align 16
+// X64-NEXT: br i1 [[TMP7]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]
+// X64: [[ATOMIC_CONT]]:
+// X64-NEXT: ret x86_fp80 [[INC]]
//
// X86-LABEL: define dso_local x86_fp80 @testinc(
// X86-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0:[0-9]+]] {
-// X86-NEXT: [[ENTRY:.*:]]
-// X86-NEXT: [[RETVAL:%.*]] = alloca x86_fp80, align 4
+// X86-NEXT: [[ENTRY:.*]]:
// X86-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 4
+// X86-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 4
+// X86-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 4
+// X86-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 4
// X86-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 4
// X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4
-// X86-NEXT: [[TMP1:%.*]] = atomicrmw fadd ptr [[TMP0]], float 1.000000e+00 seq_cst, align 4
-// X86-NEXT: [[TMP2:%.*]] = fadd float [[TMP1]], 1.000000e+00
-// X86-NEXT: store float [[TMP2]], ptr [[RETVAL]], align 4
-// X86-NEXT: [[TMP3:%.*]] = load x86_fp80, ptr [[RETVAL]], align 4
-// X86-NEXT: ret x86_fp80 [[TMP3]]
+// X86-NEXT: call void @__atomic_load(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP]], i32 noundef 5)
+// X86-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 4
+// X86-NEXT: br label %[[ATOMIC_OP:.*]]
+// X86: [[ATOMIC_OP]]:
+// X86-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP3:%.*]], %[[ATOMIC_OP]] ]
+// X86-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP2]], 0xK3FFF8000000000000000
+// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)
+// X86-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 4
+// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)
+// X86-NEXT: store x86_fp80 [[INC]], ptr [[ATOMIC_TEMP2]], align 4
+// X86-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP1]], ptr noundef [[ATOMIC_TEMP2]], i32 noundef 5, i32 noundef 5)
+// X86-NEXT: [[TMP3]] = load x86_fp80, ptr [[ATOMIC_TEMP1]], align 4
+// X86-NEXT: br i1 [[CALL]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]
+// X86: [[ATOMIC_CONT]]:
+// X86-NEXT: ret x86_fp80 [[INC]]
//
long double testinc(_Atomic long double *addr) {
@@ -35,27 +66,60 @@ long double testinc(_Atomic long double *addr) {
// X64-LABEL: define dso_local x86_fp80 @testdec(
// X64-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {
-// X64-NEXT: [[ENTRY:.*:]]
-// X64-NEXT: [[RETVAL:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ENTRY:.*]]:
// X64-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 8
+// X64-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca x86_fp80, align 16
// X64-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 8
// X64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 8
-// X64-NEXT: [[TMP1:%.*]] = atomicrmw fsub ptr [[TMP0]], float 1.000000e+00 seq_cst, align 16
-// X64-NEXT: store float [[TMP1]], ptr [[RETVAL]], align 16
-// X64-NEXT: [[TMP2:%.*]] = load x86_fp80, ptr [[RETVAL]], align 16
-// X64-NEXT: ret x86_fp80 [[TMP2]]
+// X64-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i128, ptr [[TMP0]] seq_cst, align 16
+// X64-NEXT: store i128 [[ATOMIC_LOAD]], ptr [[ATOMIC_TEMP]], align 16
+// X64-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 16
+// X64-NEXT: br label %[[ATOMIC_OP:.*]]
+// X64: [[ATOMIC_OP]]:
+// X64-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP8:%.*]], %[[ATOMIC_OP]] ]
+// X64-NEXT: [[DEC:%.*]] = fadd x86_fp80 [[TMP2]], 0xKBFFF8000000000000000
+// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)
+// X64-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 16
+// X64-NEXT: [[TMP3:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 16
+// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP2]], i8 0, i64 16, i1 false)
+// X64-NEXT: store x86_fp80 [[DEC]], ptr [[ATOMIC_TEMP2]], align 16
+// X64-NEXT: [[TMP4:%.*]] = load i128, ptr [[ATOMIC_TEMP2]], align 16
+// X64-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[TMP0]], i128 [[TMP3]], i128 [[TMP4]] seq_cst seq_cst, align 16
+// X64-NEXT: [[TMP6:%.*]] = extractvalue { i128, i1 } [[TMP5]], 0
+// X64-NEXT: [[TMP7:%.*]] = extractvalue { i128, i1 } [[TMP5]], 1
+// X64-NEXT: store i128 [[TMP6]], ptr [[ATOMIC_TEMP3]], align 16
+// X64-NEXT: [[TMP8]] = load x86_fp80, ptr [[ATOMIC_TEMP3]], align 16
+// X64-NEXT: br i1 [[TMP7]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]
+// X64: [[ATOMIC_CONT]]:
+// X64-NEXT: ret x86_fp80 [[TMP1]]
//
// X86-LABEL: define dso_local x86_fp80 @testdec(
// X86-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {
-// X86-NEXT: [[ENTRY:.*:]]
-// X86-NEXT: [[RETVAL:%.*]] = alloca x86_fp80, align 4
+// X86-NEXT: [[ENTRY:.*]]:
// X86-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 4
+// X86-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 4
+// X86-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 4
+// X86-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 4
// X86-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 4
// X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4
-// X86-NEXT: [[TMP1:%.*]] = atomicrmw fsub ptr [[TMP0]], float 1.000000e+00 seq_cst, align 4
-// X86-NEXT: store float [[TMP1]], ptr [[RETVAL]], align 4
-// X86-NEXT: [[TMP2:%.*]] = load x86_fp80, ptr [[RETVAL]], align 4
-// X86-NEXT: ret x86_fp80 [[TMP2]]
+// X86-NEXT: call void @__atomic_load(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP]], i32 noundef 5)
+// X86-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 4
+// X86-NEXT: br label %[[ATOMIC_OP:.*]]
+// X86: [[ATOMIC_OP]]:
+// X86-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP3:%.*]], %[[ATOMIC_OP]] ]
+// X86-NEXT: [[DEC:%.*]] = fadd x86_fp80 [[TMP2]], 0xKBFFF8000000000000000
+// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)
+// X86-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 4
+// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)
+// X86-NEXT: store x86_fp80 [[DEC]], ptr [[ATOMIC_TEMP2]], align 4
+// X86-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP1]], ptr noundef [[ATOMIC_TEMP2]], i32 noundef 5, i32 noundef 5)
+// X86-NEXT: [[TMP3]] = load x86_fp80, ptr [[ATOMIC_TEMP1]], align 4
+// X86-NEXT: br i1 [[CALL]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]
+// X86: [[ATOMIC_CONT]]:
+// X86-NEXT: ret x86_fp80 [[TMP1]]
//
long double testdec(_Atomic long double *addr) {
@@ -175,29 +239,60 @@ long double testassign(_Atomic long double *addr) {
// X64-LABEL: define dso_local x86_fp80 @test_volatile_inc(
// X64-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {
-// X64-NEXT: [[ENTRY:.*:]]
-// X64-NEXT: [[RETVAL:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ENTRY:.*]]:
// X64-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 8
+// X64-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca x86_fp80, align 16
// X64-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 8
// X64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 8
-// X64-NEXT: [[TMP1:%.*]] = atomicrmw fadd ptr [[TMP0]], float 1.000000e+00 seq_cst, align 16
-// X64-NEXT: [[TMP2:%.*]] = fadd float [[TMP1]], 1.000000e+00
-// X64-NEXT: store float [[TMP2]], ptr [[RETVAL]], align 16
-// X64-NEXT: [[TMP3:%.*]] = load x86_fp80, ptr [[RETVAL]], align 16
-// X64-NEXT: ret x86_fp80 [[TMP3]]
+// X64-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic volatile i128, ptr [[TMP0]] seq_cst, align 16
+// X64-NEXT: store i128 [[ATOMIC_LOAD]], ptr [[ATOMIC_TEMP]], align 16
+// X64-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 16
+// X64-NEXT: br label %[[ATOMIC_OP:.*]]
+// X64: [[ATOMIC_OP]]:
+// X64-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP8:%.*]], %[[ATOMIC_OP]] ]
+// X64-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP2]], 0xK3FFF8000000000000000
+// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)
+// X64-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 16
+// X64-NEXT: [[TMP3:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 16
+// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP2]], i8 0, i64 16, i1 false)
+// X64-NEXT: store x86_fp80 [[INC]], ptr [[ATOMIC_TEMP2]], align 16
+// X64-NEXT: [[TMP4:%.*]] = load i128, ptr [[ATOMIC_TEMP2]], align 16
+// X64-NEXT: [[TMP5:%.*]] = cmpxchg volatile ptr [[TMP0]], i128 [[TMP3]], i128 [[TMP4]] seq_cst seq_cst, align 16
+// X64-NEXT: [[TMP6:%.*]] = extractvalue { i128, i1 } [[TMP5]], 0
+// X64-NEXT: [[TMP7:%.*]] = extractvalue { i128, i1 } [[TMP5]], 1
+// X64-NEXT: store i128 [[TMP6]], ptr [[ATOMIC_TEMP3]], align 16
+// X64-NEXT: [[TMP8]] = load x86_fp80, ptr [[ATOMIC_TEMP3]], align 16
+// X64-NEXT: br i1 [[TMP7]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]
+// X64: [[ATOMIC_CONT]]:
+// X64-NEXT: ret x86_fp80 [[INC]]
//
// X86-LABEL: define dso_local x86_fp80 @test_volatile_inc(
// X86-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {
-// X86-NEXT: [[ENTRY:.*:]]
-// X86-NEXT: [[RETVAL:%.*]] = alloca x86_fp80, align 4
+// X86-NEXT: [[ENTRY:.*]]:
// X86-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 4
+// X86-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 4
+// X86-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 4
+// X86-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 4
// X86-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 4
// X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4
-// X86-NEXT: [[TMP1:%.*]] = atomicrmw fadd ptr [[TMP0]], float 1.000000e+00 seq_cst, align 4
-// X86-NEXT: [[TMP2:%.*]] = fadd float [[TMP1]], 1.000000e+00
-// X86-NEXT: store float [[TMP2]], ptr [[RETVAL]], align 4
-// X86-NEXT: [[TMP3:%.*]] = load x86_fp80, ptr [[RETVAL]], align 4
-// X86-NEXT: ret x86_fp80 [[TMP3]]
+// X86-NEXT: call void @__atomic_load(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP]], i32 noundef 5)
+// X86-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 4
+// X86-NEXT: br label %[[ATOMIC_OP:.*]]
+// X86: [[ATOMIC_OP]]:
+// X86-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP3:%.*]], %[[ATOMIC_OP]] ]
+// X86-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP2]], 0xK3FFF8000000000000000
+// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)
+// X86-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 4
+// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)
+// X86-NEXT: store x86_fp80 [[INC]], ptr [[ATOMIC_TEMP2]], align 4
+// X86-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP1]], ptr noundef [[ATOMIC_TEMP2]], i32 noundef 5, i32 noundef 5)
+// X86-NEXT: [[TMP3]] = load x86_fp80, ptr [[ATOMIC_TEMP1]], align 4
+// X86-NEXT: br i1 [[CALL]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]
+// X86: [[ATOMIC_CONT]]:
+// X86-NEXT: ret x86_fp80 [[INC]]
//
long double test_volatile_inc(volatile _Atomic long double *addr) {
return ++*addr;
@@ -205,27 +300,60 @@ long double test_volatile_inc(volatile _Atomic long double *addr) {
// X64-LABEL: define dso_local x86_fp80 @test_volatile_dec(
// X64-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {
-// X64-NEXT: [[ENTRY:.*:]]
-// X64-NEXT: [[RETVAL:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ENTRY:.*]]:
// X64-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 8
+// X64-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca x86_fp80, align 16
// X64-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 8
// X64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 8
-// X64-NEXT: [[TMP1:%.*]] = atomicrmw fsub ptr [[TMP0]], float 1.000000e+00 seq_cst, align 16
-// X64-NEXT: store float [[TMP1]], ptr [[RETVAL]], align 16
-// X64-NEXT: [[TMP2:%.*]] = load x86_fp80, ptr [[RETVAL]], align 16
-// X64-NEXT: ret x86_fp80 [[TMP2]]
+// X64-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic volatile i128, ptr [[TMP0]] seq_cst, align 16
+// X64-NEXT: store i128 [[ATOMIC_LOAD]], ptr [[ATOMIC_TEMP]], align 16
+// X64-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 16
+// X64-NEXT: br label %[[ATOMIC_OP:.*]]
+// X64: [[ATOMIC_OP]]:
+// X64-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP8:%.*]], %[[ATOMIC_OP]] ]
+// X64-NEXT: [[DEC:%.*]] = fadd x86_fp80 [[TMP2]], 0xKBFFF8000000000000000
+// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)
+// X64-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 16
+// X64-NEXT: [[TMP3:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 16
+// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP2]], i8 0, i64 16, i1 false)
+// X64-NEXT: store x86_fp80 [[DEC]], ptr [[ATOMIC_TEMP2]], align 16
+// X64-NEXT: [[TMP4:%.*]] = load i128, ptr [[ATOMIC_TEMP2]], align 16
+// X64-NEXT: [[TMP5:%.*]] = cmpxchg volatile ptr [[TMP0]], i128 [[TMP3]], i128 [[TMP4]] seq_cst seq_cst, align 16
+// X64-NEXT: [[TMP6:%.*]] = extractvalue { i128, i1 } [[TMP5]], 0
+// X64-NEXT: [[TMP7:%.*]] = extractvalue { i128, i1 } [[TMP5]], 1
+// X64-NEXT: store i128 [[TMP6]], ptr [[ATOMIC_TEMP3]], align 16
+// X64-NEXT: [[TMP8]] = load x86_fp80, ptr [[ATOMIC_TEMP3]], align 16
+// X64-NEXT: br i1 [[TMP7]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]
+// X64: [[ATOMIC_CONT]]:
+// X64-NEXT: ret x86_fp80 [[TMP1]]
//
// X86-LABEL: define dso_local x86_fp80 @test_volatile_dec(
// X86-SAME: ptr noundef [[ADDR:%.*]]) #[[ATTR0]] {
-// X86-NEXT: [[ENTRY:.*:]]
-// X86-NEXT: [[RETVAL:%.*]] = alloca x86_fp80, align 4
+// X86-NEXT: [[ENTRY:.*]]:
// X86-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 4
+// X86-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 4
+// X86-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 4
+// X86-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 4
// X86-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR]], align 4
// X86-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR]], align 4
-// X86-NEXT: [[TMP1:%.*]] = atomicrmw fsub ptr [[TMP0]], float 1.000000e+00 seq_cst, align 4
-// X86-NEXT: store float [[TMP1]], ptr [[RETVAL]], align 4
-// X86-NEXT: [[TMP2:%.*]] = load x86_fp80, ptr [[RETVAL]], align 4
-// X86-NEXT: ret x86_fp80 [[TMP2]]
+// X86-NEXT: call void @__atomic_load(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP]], i32 noundef 5)
+// X86-NEXT: [[TMP1:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 4
+// X86-NEXT: br label %[[ATOMIC_OP:.*]]
+// X86: [[ATOMIC_OP]]:
+// X86-NEXT: [[TMP2:%.*]] = phi x86_fp80 [ [[TMP1]], %[[ENTRY]] ], [ [[TMP3:%.*]], %[[ATOMIC_OP]] ]
+// X86-NEXT: [[DEC:%.*]] = fadd x86_fp80 [[TMP2]], 0xKBFFF8000000000000000
+// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)
+// X86-NEXT: store x86_fp80 [[TMP2]], ptr [[ATOMIC_TEMP1]], align 4
+// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)
+// X86-NEXT: store x86_fp80 [[DEC]], ptr [[ATOMIC_TEMP2]], align 4
+// X86-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP1]], ptr noundef [[ATOMIC_TEMP2]], i32 noundef 5, i32 noundef 5)
+// X86-NEXT: [[TMP3]] = load x86_fp80, ptr [[ATOMIC_TEMP1]], align 4
+// X86-NEXT: br i1 [[CALL]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]
+// X86: [[ATOMIC_CONT]]:
+// X86-NEXT: ret x86_fp80 [[TMP1]]
//
long double test_volatile_dec(volatile _Atomic long double *addr) {
return (*addr)--;
@@ -341,3 +469,64 @@ long double test_volatile_assign(volatile _Atomic long double *addr) {
return *addr;
}
+
+// X64-LABEL: define dso_local i32 @pr107054(
+// X64-SAME: ) #[[ATTR0]] {
+// X64-NEXT: [[ENTRY:.*]]:
+// X64-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca x86_fp80, align 16
+// X64-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i128, ptr @pr107054.n seq_cst, align 16
+// X64-NEXT: store i128 [[ATOMIC_LOAD]], ptr [[ATOMIC_TEMP]], align 16
+// X64-NEXT: [[TMP0:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 16
+// X64-NEXT: br label %[[ATOMIC_OP:.*]]
+// X64: [[ATOMIC_OP]]:
+// X64-NEXT: [[TMP1:%.*]] = phi x86_fp80 [ [[TMP0]], %[[ENTRY]] ], [ [[TMP7:%.*]], %[[ATOMIC_OP]] ]
+// X64-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP1]], 0xK3FFF8000000000000000
+// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP1]], i8 0, i64 16, i1 false)
+// X64-NEXT: store x86_fp80 [[TMP1]], ptr [[ATOMIC_TEMP1]], align 16
+// X64-NEXT: [[TMP2:%.*]] = load i128, ptr [[ATOMIC_TEMP1]], align 16
+// X64-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[ATOMIC_TEMP2]], i8 0, i64 16, i1 false)
+// X64-NEXT: store x86_fp80 [[INC]], ptr [[ATOMIC_TEMP2]], align 16
+// X64-NEXT: [[TMP3:%.*]] = load i128, ptr [[ATOMIC_TEMP2]], align 16
+// X64-NEXT: [[TMP4:%.*]] = cmpxchg ptr @pr107054.n, i128 [[TMP2]], i128 [[TMP3]] seq_cst seq_cst, align 16
+// X64-NEXT: [[TMP5:%.*]] = extractvalue { i128, i1 } [[TMP4]], 0
+// X64-NEXT: [[TMP6:%.*]] = extractvalue { i128, i1 } [[TMP4]], 1
+// X64-NEXT: store i128 [[TMP5]], ptr [[ATOMIC_TEMP3]], align 16
+// X64-NEXT: [[TMP7]] = load x86_fp80, ptr [[ATOMIC_TEMP3]], align 16
+// X64-NEXT: br i1 [[TMP6]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]
+// X64: [[ATOMIC_CONT]]:
+// X64-NEXT: [[CMP:%.*]] = fcmp oeq x86_fp80 [[INC]], 0xK3FFF8000000000000000
+// X64-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i32
+// X64-NEXT: ret i32 [[CONV]]
+//
+// X86-LABEL: define dso_local i32 @pr107054(
+// X86-SAME: ) #[[ATTR0]] {
+// X86-NEXT: [[ENTRY:.*]]:
+// X86-NEXT: [[ATOMIC_TEMP:%.*]] = alloca x86_fp80, align 4
+// X86-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca x86_fp80, align 4
+// X86-NEXT: [[ATOMIC_TEMP2:%.*]] = alloca x86_fp80, align 4
+// X86-NEXT: call void @__atomic_load(i32 noundef 12, ptr noundef @pr107054.n, ptr noundef [[ATOMIC_TEMP]], i32 noundef 5)
+// X86-NEXT: [[TMP0:%.*]] = load x86_fp80, ptr [[ATOMIC_TEMP]], align 4
+// X86-NEXT: br label %[[ATOMIC_OP:.*]]
+// X86: [[ATOMIC_OP]]:
+// X86-NEXT: [[TMP1:%.*]] = phi x86_fp80 [ [[TMP0]], %[[ENTRY]] ], [ [[TMP2:%.*]], %[[ATOMIC_OP]] ]
+// X86-NEXT: [[INC:%.*]] = fadd x86_fp80 [[TMP1]], 0xK3FFF8000000000000000
+// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], i8 0, i64 12, i1 false)
+// X86-NEXT: store x86_fp80 [[TMP1]], ptr [[ATOMIC_TEMP1]], align 4
+// X86-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[ATOMIC_TEMP2]], i8 0, i64 12, i1 false)
+// X86-NEXT: store x86_fp80 [[INC]], ptr [[ATOMIC_TEMP2]], align 4
+// X86-NEXT: [[CALL:%.*]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, ptr noundef @pr107054.n, ptr noundef [[ATOMIC_TEMP1]], ptr noundef [[ATOMIC_TEMP2]], i32 noundef 5, i32 noundef 5)
+// X86-NEXT: [[TMP2]] = load x86_fp80, ptr [[ATOMIC_TEMP1]], align 4
+// X86-NEXT: br i1 [[CALL]], label %[[ATOMIC_CONT:.*]], label %[[ATOMIC_OP]]
+// X86: [[ATOMIC_CONT]]:
+// X86-NEXT: [[CMP:%.*]] = fcmp oeq x86_fp80 [[INC]], 0xK3FFF8000000000000000
+// X86-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i32
+// X86-NEXT: ret i32 [[CONV]]
+//
+int pr107054()
+{
+ static _Atomic long double n;
+ return (++n) == 1;
+}
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