[llvm-branch-commits] [llvm] [AArch64] Define high bits of FPR and GPR registers. (PR #114263)
Sander de Smalen via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Oct 31 10:50:41 PDT 2024
================
@@ -424,6 +424,58 @@ AArch64RegisterInfo::explainReservedReg(const MachineFunction &MF,
return {};
}
+static SmallVector<MCPhysReg> ReservedHi = {
----------------
sdesmalen-arm wrote:
Without marking the registers as reserved, then for the example below:
```
---
name: sv2i64
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $q0, $q1
%0:fpr128 = COPY $q0
%1:fpr128 = COPY $q1
%35:gpr64 = COPY %0.dsub
%36:gpr64 = COPY %1.dsub
%9:gpr64 = SDIVXr %35, %36
%37:gpr64 = UMOVvi64 %0, 1
%38:gpr64 = UMOVvi64 %1, 1
%10:gpr64 = SDIVXr %37, %38
%19:fpr128 = INSvi64gpr undef %19, 0, %9
%19:fpr128 = INSvi64gpr %19, 1, %10
%39:gpr64 = COPY %19.dsub
%24:gpr64 = MADDXrrr %39, %36, $xzr
%41:gpr64 = UMOVvi64 %19, 1
%25:gpr64 = MADDXrrr %41, %38, $xzr
%34:fpr128 = INSvi64gpr undef %34, 0, %24
%34:fpr128 = INSvi64gpr %34, 1, %25
%2:fpr128 = SUBv2i64 %0, %34
$q0 = COPY %2
RET_ReallyLR implicit $q0
...
```
When I run this with:
```
llc -global-isel -verify-machineinstrs -run-pass=machine-scheduler
```
It fails with:
```
Use of $xzr does not have a corresponding definition on every path:
216r %10:gpr64 = MADDXrrr %9:gpr64, %3:gpr64, $xzr
LLVM ERROR: Use not jointly dominated by defs.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0. Program arguments: ./bin/llc -global-isel -verify-machineinstrs -run-pass=machine-scheduler /tmp/t.mir -o -
1. Running pass 'Function Pass Manager' on module '/tmp/t.mir'.
2. Running pass 'Machine Instruction Scheduler' on function '@sv2i64'
...
#8 0x0000ffff80062b7c llvm::LiveRangeCalc::findReachingDefs(llvm::LiveRange&, llvm::MachineBasicBlock&, llvm::SlotIndex, unsigned int, llvm::ArrayRef<llvm::SlotIndex>)
#9 0x0000ffff80063e94 llvm::LiveRangeCalc::extend(llvm::LiveRange&, llvm::SlotIndex, unsigned int, llvm::ArrayRef<llvm::SlotIndex>)
#10 0x0000ffff80064a18 llvm::LiveIntervalCalc::extendToUses(llvm::LiveRange&, llvm::Register, llvm::LaneBitmask, llvm::LiveInterval*)
#11 0x0000ffff8003e82c llvm::LiveIntervals::computeRegUnitRange(llvm::LiveRange&, unsigned int)
#12 0x0000ffff80044cdc llvm::LiveIntervals::HMEditor::updateAllRanges(llvm::MachineInstr*)
#13 0x0000ffff8004848c llvm::LiveIntervals::handleMove(llvm::MachineInstr&, bool)
#14 0x0000ffff801f44ec llvm::ScheduleDAGMI::moveInstruction(llvm::MachineInstr*, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>)
#15 0x0000ffff801fdb58 llvm::ScheduleDAGMILive::scheduleMI(llvm::SUnit*, bool)
#16 0x0000ffff8020b214 llvm::ScheduleDAGMILive::schedule()
#17 0x0000ffff801f0934 (anonymous namespace)::MachineSchedulerBase::scheduleRegions(llvm::ScheduleDAGInstrs&, bool) (.isra.0) MachineScheduler.cpp:0:0
```
https://github.com/llvm/llvm-project/pull/114263
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