[llvm-branch-commits] [llvm] [RISCV][NFC] refactor CFI emitting (PR #114227)
Sam Elliott via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Oct 30 12:19:56 PDT 2024
================
@@ -27,6 +27,102 @@
using namespace llvm;
+static unsigned getCaleeSavedRVVNumRegs(const Register &BaseReg) {
+ return RISCV::VRRegClass.contains(BaseReg) ? 1
+ : RISCV::VRM2RegClass.contains(BaseReg) ? 2
+ : RISCV::VRM4RegClass.contains(BaseReg) ? 4
+ : 8;
+}
+
+static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI,
+ const Register &Reg) {
+ MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
+ // If it's not a grouped vector register, it doesn't have subregister, so
+ // the base register is just itself.
+ if (BaseReg == RISCV::NoRegister)
+ BaseReg = Reg;
+ return BaseReg;
+}
+
+namespace {
+
+struct CFIRestoreRegisterEmitter {
+ CFIRestoreRegisterEmitter(MachineFunction &, const RISCVSubtarget &) {};
+
+ void emit(MachineFunction &MF, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI,
+ const RISCVInstrInfo &TII, const DebugLoc &DL,
+ const CalleeSavedInfo &CS) const {
+ Register Reg = CS.getReg();
+ unsigned CFIIndex = MF.addFrameInst(
+ MCCFIInstruction::createRestore(nullptr, RI.getDwarfRegNum(Reg, true)));
+ BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
+ .addCFIIndex(CFIIndex)
+ .setMIFlag(MachineInstr::FrameDestroy);
+ }
+};
+
+class CFIStoreRegisterEmitter {
----------------
lenary wrote:
```suggestion
class CFISaveRegisterEmitter {
```
I think it would be clearer to use "Save" as the opposite of "Restore", rather than "Store" vs "Restore".
https://github.com/llvm/llvm-project/pull/114227
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