[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: RBLegalize (PR #112864)

Petar Avramovic via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Mon Oct 21 02:02:34 PDT 2024


================
@@ -0,0 +1,118 @@
+//===- AMDGPURBLegalizeHelper ------------------------------------*- C++ -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPURBLEGALIZEHELPER_H
+#define LLVM_LIB_TARGET_AMDGPU_AMDGPURBLEGALIZEHELPER_H
+
+#include "AMDGPURBLegalizeRules.h"
+#include "AMDGPURegisterBankInfo.h"
+#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+
+namespace llvm {
+namespace AMDGPU {
+
+// Receives list of RegBankLLTMapingApplyID and applies register banks on all
+// operands. It is user's responsibility to provide RegBankLLTMapingApplyIDs for
+// all register operands, there is no need to specify NonReg for trailing imm
+// operands. This finishes selection of register banks if there is no need to
+// replace instruction. In other case InstApplyMethod will create new
+// instruction(s).
+class RegBankLegalizeHelper {
+  MachineIRBuilder &B;
+  MachineRegisterInfo &MRI;
+  const MachineUniformityInfo &MUI;
+  const RegisterBankInfo &RBI;
+  const RegBankLegalizeRules &RBLRules;
+  const RegisterBank *SgprRB;
+  const RegisterBank *VgprRB;
+  const RegisterBank *VccRB;
+
+  LLT S1 = LLT::scalar(1);
+  LLT S16 = LLT::scalar(16);
+  LLT S32 = LLT::scalar(32);
+  LLT S64 = LLT::scalar(64);
+  LLT V2S16 = LLT::fixed_vector(2, 16);
+  LLT V2S32 = LLT::fixed_vector(2, 32);
+  LLT V3S32 = LLT::fixed_vector(3, 32);
+  LLT V4S32 = LLT::fixed_vector(4, 32);
+  LLT V6S32 = LLT::fixed_vector(6, 32);
+  LLT V7S32 = LLT::fixed_vector(7, 32);
+  LLT V8S32 = LLT::fixed_vector(8, 32);
+
+  LLT V3S64 = LLT::fixed_vector(3, 64);
+  LLT V4S64 = LLT::fixed_vector(4, 64);
+  LLT V16S64 = LLT::fixed_vector(16, 64);
+
+  LLT P1 = LLT::pointer(1, 64);
+  LLT P4 = LLT::pointer(4, 64);
+  LLT P6 = LLT::pointer(6, 32);
+
+public:
+  RegBankLegalizeHelper(MachineIRBuilder &B, MachineRegisterInfo &MRI,
+                        const MachineUniformityInfo &MUI,
+                        const RegisterBankInfo &RBI,
+                        const RegBankLegalizeRules &RBLRules)
+      : B(B), MRI(MRI), MUI(MUI), RBI(RBI), RBLRules(RBLRules),
+        SgprRB(&RBI.getRegBank(AMDGPU::SGPRRegBankID)),
+        VgprRB(&RBI.getRegBank(AMDGPU::VGPRRegBankID)),
+        VccRB(&RBI.getRegBank(AMDGPU::VCCRegBankID)) {};
+
+  bool findRuleAndApplyMapping(MachineInstr &MI);
+
+  // Manual apply helpers.
+  void applyMappingPHI(MachineInstr &MI);
+  void applyMappingTrivial(MachineInstr &MI);
+
+private:
+  Register createVgpr(LLT Ty) {
+    return MRI.createVirtualRegister({VgprRB, Ty});
+  }
+  Register createSgpr(LLT Ty) {
+    return MRI.createVirtualRegister({SgprRB, Ty});
+  }
+  Register createVcc() { return MRI.createVirtualRegister({VccRB, S1}); }
+
+  const RegisterBank *getRegBank(Register Reg) {
+    const RegisterBank *RB = MRI.getRegBankOrNull(Reg);
+    // This assert is not guaranteed by default. RB-select ensures that all
+    // instructions that we want to RB-legalize have reg banks on all registers.
+    // There might be a few exceptions. Workaround for them is to not write
+    // 'mapping' for register operand that is expected to have reg class.
+    assert(RB);
+    return RB;
----------------
petar-avramovic wrote:

> What about the assigned register class case?

I intended for RBLegalize to work with register banks only.
RBSelect is meant to deal with assigned register classes:
- on def in first loop
// Assign register banks to ALL def registers on G_ instructions.
- on use in second loop
// Reassign uses of G_ instructions to only have register banks.


https://github.com/llvm/llvm-project/pull/112864


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