[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: RBLegalize (PR #112864)

[Petar Avramovic via llvm-branch-commits]

================
@@ -0,0 +1,334 @@
+//===-- AMDGPURBLegalizeRules.cpp -----------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+/// Definitions of RBLegalize Rules for all opcodes.
+/// Implementation of container for all the Rules and search.
+/// Fast search for most common case when Rule.Predicate checks LLT and
+/// uniformity of register in operand 0.
+//
+//===----------------------------------------------------------------------===//
+
+#include "AMDGPURBLegalizeRules.h"
+#include "GCNSubtarget.h"
+#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
+#include "llvm/IR/IntrinsicsAMDGPU.h"
+
+using namespace llvm;
+using namespace AMDGPU;
+
+RegBankLLTMapping::RegBankLLTMapping(
+    std::initializer_list<RegBankLLTMapingApplyID> DstOpMappingList,
+    std::initializer_list<RegBankLLTMapingApplyID> SrcOpMappingList,
+    LoweringMethodID LoweringMethod)
+    : DstOpMapping(DstOpMappingList), SrcOpMapping(SrcOpMappingList),
+      LoweringMethod(LoweringMethod) {}
+
+PredicateMapping::PredicateMapping(
+    std::initializer_list<UniformityLLTOpPredicateID> OpList,
+    std::function<bool(const MachineInstr &)> TestFunc)
+    : OpUniformityAndTypes(OpList), TestFunc(TestFunc) {}
+
+bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
+                           const MachineUniformityInfo &MUI,
+                           const MachineRegisterInfo &MRI) {
+  switch (UniID) {
+  case S1:
+    return MRI.getType(Reg) == LLT::scalar(1);
+  case S16:
+    return MRI.getType(Reg) == LLT::scalar(16);
+  case S32:
+    return MRI.getType(Reg) == LLT::scalar(32);
+  case S64:
+    return MRI.getType(Reg) == LLT::scalar(64);
+  case P1:
+    return MRI.getType(Reg) == LLT::pointer(1, 64);
+
+  case UniS1:
+    return MRI.getType(Reg) == LLT::scalar(1) && MUI.isUniform(Reg);
+  case UniS16:
+    return MRI.getType(Reg) == LLT::scalar(16) && MUI.isUniform(Reg);
+  case UniS32:
+    return MRI.getType(Reg) == LLT::scalar(32) && MUI.isUniform(Reg);
+  case UniS64:
+    return MRI.getType(Reg) == LLT::scalar(64) && MUI.isUniform(Reg);
+
+  case DivS1:
+    return MRI.getType(Reg) == LLT::scalar(1) && MUI.isDivergent(Reg);
+  case DivS32:
+    return MRI.getType(Reg) == LLT::scalar(32) && MUI.isDivergent(Reg);
+  case DivS64:
+    return MRI.getType(Reg) == LLT::scalar(64) && MUI.isDivergent(Reg);
+  case DivP1:
+    return MRI.getType(Reg) == LLT::pointer(1, 64) && MUI.isDivergent(Reg);
+
+  case _:
----------------
petar-avramovic wrote:

That is "don't check anything", for example used in:
```
  addRulesForIOpcs({amdgcn_frexp_exp})
      .Any({{DivS32, _, S32}, {{Vgpr32}, {IntrId, Vgpr32}}})
      .Any({{DivS32, _, S64}, {{Vgpr32}, {IntrId, Vgpr64}}});
```
it is used to skip non-virtual-registers(intrinsics ID, imm, physical register or $noreg) in PredicateMapping when writing rules for amdgpu-intrinsics

https://github.com/llvm/llvm-project/pull/112864