[llvm-branch-commits] [clang] 3217472 - Revert "[RISCV][FMV] Support target_version (#99040)"
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Oct 3 20:55:48 PDT 2024
Author: Piyou Chen
Date: 2024-10-04T11:55:45+08:00
New Revision: 32174720649068de7c4ef97a484d777dba72e65c
URL: https://github.com/llvm/llvm-project/commit/32174720649068de7c4ef97a484d777dba72e65c
DIFF: https://github.com/llvm/llvm-project/commit/32174720649068de7c4ef97a484d777dba72e65c.diff
LOG: Revert "[RISCV][FMV] Support target_version (#99040)"
This reverts commit 7ab488e92c39c813a50cb4fd6587e7afc161c7d5.
Added:
Modified:
clang/lib/AST/ASTContext.cpp
clang/lib/CodeGen/CodeGenModule.cpp
clang/lib/Sema/SemaDecl.cpp
clang/lib/Sema/SemaDeclAttr.cpp
Removed:
clang/test/CodeGen/attr-target-version-riscv-invalid.c
clang/test/CodeGen/attr-target-version-riscv.c
clang/test/CodeGenCXX/attr-target-version-riscv.cpp
clang/test/SemaCXX/attr-target-version-riscv.cpp
################################################################################
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 034fbbe0bc7829..a81429ad6a2380 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -14325,17 +14325,9 @@ void ASTContext::getFunctionFeatureMap(llvm::StringMap<bool> &FeatureMap,
Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU, Features);
}
} else if (const auto *TV = FD->getAttr<TargetVersionAttr>()) {
- std::vector<std::string> Features;
- if (Target->getTriple().isRISCV()) {
- ParsedTargetAttr ParsedAttr = Target->parseTargetAttr(TV->getName());
- Features.insert(Features.begin(), ParsedAttr.Features.begin(),
- ParsedAttr.Features.end());
- } else {
- assert(Target->getTriple().isAArch64());
- llvm::SmallVector<StringRef, 8> Feats;
- TV->getFeatures(Feats);
- Features = getFMVBackendFeaturesFor(Feats);
- }
+ llvm::SmallVector<StringRef, 8> Feats;
+ TV->getFeatures(Feats);
+ std::vector<std::string> Features = getFMVBackendFeaturesFor(Feats);
Features.insert(Features.begin(),
Target->getTargetOpts().FeaturesAsWritten.begin(),
Target->getTargetOpts().FeaturesAsWritten.end());
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp
index 5ba098144a74e7..25c1c496a4f27f 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -4287,13 +4287,8 @@ void CodeGenModule::emitMultiVersionFunctions() {
} else if (const auto *TVA = CurFD->getAttr<TargetVersionAttr>()) {
if (TVA->isDefaultVersion() && IsDefined)
ShouldEmitResolver = true;
+ TVA->getFeatures(Feats);
llvm::Function *Func = createFunction(CurFD);
- if (getTarget().getTriple().isRISCV()) {
- Feats.push_back(TVA->getName());
- } else {
- assert(getTarget().getTriple().isAArch64());
- TVA->getFeatures(Feats);
- }
Options.emplace_back(Func, /*Architecture*/ "", Feats);
} else if (const auto *TC = CurFD->getAttr<TargetClonesAttr>()) {
if (IsDefined)
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index 21f25a2ea09eb0..2bf610746bc317 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -10329,8 +10329,7 @@ Sema::ActOnFunctionDeclarator(Scope *S, Declarator &D, DeclContext *DC,
// Handle attributes.
ProcessDeclAttributes(S, NewFD, D);
const auto *NewTVA = NewFD->getAttr<TargetVersionAttr>();
- if (Context.getTargetInfo().getTriple().isAArch64() && NewTVA &&
- !NewTVA->isDefaultVersion() &&
+ if (NewTVA && !NewTVA->isDefaultVersion() &&
!Context.getTargetInfo().hasFeature("fmv")) {
// Don't add to scope fmv functions declarations if fmv disabled
AddToScope = false;
@@ -11039,15 +11038,7 @@ static bool CheckMultiVersionValue(Sema &S, const FunctionDecl *FD) {
if (TVA) {
llvm::SmallVector<StringRef, 8> Feats;
- if (S.getASTContext().getTargetInfo().getTriple().isRISCV()) {
- ParsedTargetAttr ParseInfo =
- S.getASTContext().getTargetInfo().parseTargetAttr(TVA->getName());
- for (auto &Feat : ParseInfo.Features)
- Feats.push_back(StringRef{Feat}.substr(1));
- } else {
- assert(S.getASTContext().getTargetInfo().getTriple().isAArch64());
- TVA->getFeatures(Feats);
- }
+ TVA->getFeatures(Feats);
for (const auto &Feat : Feats) {
if (!TargetInfo.validateCpuSupports(Feat)) {
S.Diag(FD->getLocation(), diag::err_bad_multiversion_option)
@@ -11333,8 +11324,7 @@ static bool PreviousDeclsHaveMultiVersionAttribute(const FunctionDecl *FD) {
}
static void patchDefaultTargetVersion(FunctionDecl *From, FunctionDecl *To) {
- if (!From->getASTContext().getTargetInfo().getTriple().isAArch64() &&
- !From->getASTContext().getTargetInfo().getTriple().isRISCV())
+ if (!From->getASTContext().getTargetInfo().getTriple().isAArch64())
return;
MultiVersionKind MVKindFrom = From->getMultiVersionKind();
@@ -15521,8 +15511,7 @@ Decl *Sema::ActOnStartOfFunctionDef(Scope *FnBodyScope, Decl *D,
FD->setInvalidDecl();
}
if (const auto *Attr = FD->getAttr<TargetVersionAttr>()) {
- if (Context.getTargetInfo().getTriple().isAArch64() &&
- !Context.getTargetInfo().hasFeature("fmv") &&
+ if (!Context.getTargetInfo().hasFeature("fmv") &&
!Attr->isDefaultVersion()) {
// If function multi versioning disabled skip parsing function body
// defined with non-default target_version attribute
diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp
index af983349a89b58..c9b9f3a0007daa 100644
--- a/clang/lib/Sema/SemaDeclAttr.cpp
+++ b/clang/lib/Sema/SemaDeclAttr.cpp
@@ -3040,54 +3040,6 @@ bool Sema::checkTargetVersionAttr(SourceLocation LiteralLoc, Decl *D,
enum SecondParam { None };
enum ThirdParam { Target, TargetClones, TargetVersion };
llvm::SmallVector<StringRef, 8> Features;
- if (Context.getTargetInfo().getTriple().isRISCV()) {
- llvm::SmallVector<StringRef, 8> AttrStrs;
- AttrStr.split(AttrStrs, ';');
-
- bool HasArch = false;
- bool HasPriority = false;
- bool HasDefault = false;
- bool DuplicateAttr = false;
- for (auto &AttrStr : AttrStrs) {
- // Only support arch=+ext,... syntax.
- if (AttrStr.starts_with("arch=+")) {
- if (HasArch)
- DuplicateAttr = true;
- HasArch = true;
- ParsedTargetAttr TargetAttr =
- Context.getTargetInfo().parseTargetAttr(AttrStr);
-
- if (TargetAttr.Features.empty() ||
- llvm::any_of(TargetAttr.Features, [&](const StringRef Ext) {
- return !RISCV().isValidFMVExtension(Ext);
- }))
- return Diag(LiteralLoc, diag::warn_unsupported_target_attribute)
- << Unsupported << None << AttrStr << TargetVersion;
- } else if (AttrStr.starts_with("default")) {
- if (HasDefault)
- DuplicateAttr = true;
- HasDefault = true;
- } else if (AttrStr.consume_front("priority=")) {
- if (HasPriority)
- DuplicateAttr = true;
- HasPriority = true;
- int Digit;
- if (AttrStr.getAsInteger(0, Digit))
- return Diag(LiteralLoc, diag::warn_unsupported_target_attribute)
- << Unsupported << None << AttrStr << TargetVersion;
- } else {
- return Diag(LiteralLoc, diag::warn_unsupported_target_attribute)
- << Unsupported << None << AttrStr << TargetVersion;
- }
- }
-
- if (((HasPriority || HasArch) && HasDefault) || DuplicateAttr ||
- (HasPriority && !HasArch))
- return Diag(LiteralLoc, diag::warn_unsupported_target_attribute)
- << Unsupported << None << AttrStr << TargetVersion;
-
- return false;
- }
AttrStr.split(Features, "+");
for (auto &CurFeature : Features) {
CurFeature = CurFeature.trim();
diff --git a/clang/test/CodeGen/attr-target-version-riscv-invalid.c b/clang/test/CodeGen/attr-target-version-riscv-invalid.c
deleted file mode 100644
index 0948b3bfd9ef32..00000000000000
--- a/clang/test/CodeGen/attr-target-version-riscv-invalid.c
+++ /dev/null
@@ -1,13 +0,0 @@
-// RUN: not %clang_cc1 -triple riscv64 -target-feature +i -emit-llvm -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-UNSUPPORT-OS
-
-// CHECK-UNSUPPORT-OS: error: function multiversioning is currently only supported on Linux
-__attribute__((target_version("default"))) int foo(void) {
- return 2;
-}
-
-__attribute__((target_version("arch=+c"))) int foo(void) {
- return 2;
-}
-
-
-int bar() { return foo(); }
diff --git a/clang/test/CodeGen/attr-target-version-riscv.c b/clang/test/CodeGen/attr-target-version-riscv.c
deleted file mode 100644
index 7d0e61e61542f2..00000000000000
--- a/clang/test/CodeGen/attr-target-version-riscv.c
+++ /dev/null
@@ -1,443 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --include-generated-funcs --version 4
-// RUN: %clang_cc1 -triple riscv64-linux-gnu -target-feature +i -emit-llvm -o - %s | FileCheck %s
-
-__attribute__((target_version("arch=+v"))) int foo1(void) { return 1; }
-__attribute__((target_version("default"))) int foo1(void) { return 1; }
-
-__attribute__((target_version("arch=+zbb"))) int foo2(void) { return 1; }
-__attribute__((target_version("arch=+m"))) int foo2(void) { return 1; }
-__attribute__((target_version("default"))) int foo2(void) { return 1; }
-
-__attribute__((target_version("arch=+zbb,+c"))) int foo3(void) { return 1; }
-__attribute__((target_version("arch=+m"))) int foo3(void) { return 1; }
-__attribute__((target_version("default"))) int foo3(void) { return 1; }
-
-__attribute__((target_version("arch=+zba"))) int foo4(void) { return 1; }
-__attribute__((target_version("arch=+zbb"))) int foo4(void) { return 1; }
-__attribute__((target_version("arch=+zbb,+zba"))) int foo4(void) { return 1; }
-__attribute__((target_version("default"))) int foo4(void) { return 1; }
-
-__attribute__((target_version("arch=+zba"))) int foo5(void) { return 1; }
-__attribute__((target_version("arch=+zbb,+zba"))) int foo5(void) { return 1; }
-__attribute__((target_version("arch=+zbb"))) int foo5(void) { return 1; }
-__attribute__((target_version("default"))) int foo5(void) { return 1; }
-
-__attribute__((target_version("arch=+zba"))) int foo6(void) { return 1; }
-__attribute__((target_version("arch=+zbb"))) int foo6(void) { return 1; }
-__attribute__((target_version("arch=+zbb,+zba;priority=10"))) int foo6(void) { return 1; }
-__attribute__((target_version("default"))) int foo6(void) { return 1; }
-
-__attribute__((target_version("priority=8;arch=+zba"))) int foo7(void) { return 1; }
-__attribute__((target_version("arch=+zbb;priority=9"))) int foo7(void) { return 1; }
-__attribute__((target_version("arch=+zbb,+zba;priority=10"))) int foo7(void) { return 1; }
-__attribute__((target_version("default"))) int foo7(void) { return 1; }
-
-__attribute__((target_version("priority=-1;arch=+zba"))) int foo8(void) { return 1; }
-__attribute__((target_version("arch=+zbb;priority=-2"))) int foo8(void) { return 1; }
-__attribute__((target_version("arch=+zbb,+zba;priority=3"))) int foo8(void) { return 1; }
-__attribute__((target_version("default"))) int foo8(void) { return 1; }
-
-int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7() + foo8(); }
-//.
-// CHECK: @__riscv_feature_bits = external dso_local global { i32, [2 x i64] }
-// CHECK: @foo1 = weak_odr ifunc i32 (), ptr @foo1.resolver
-// CHECK: @foo2 = weak_odr ifunc i32 (), ptr @foo2.resolver
-// CHECK: @foo3 = weak_odr ifunc i32 (), ptr @foo3.resolver
-// CHECK: @foo4 = weak_odr ifunc i32 (), ptr @foo4.resolver
-// CHECK: @foo5 = weak_odr ifunc i32 (), ptr @foo5.resolver
-// CHECK: @foo6 = weak_odr ifunc i32 (), ptr @foo6.resolver
-// CHECK: @foo7 = weak_odr ifunc i32 (), ptr @foo7.resolver
-// CHECK: @foo8 = weak_odr ifunc i32 (), ptr @foo8.resolver
-//.
-// CHECK-LABEL: define dso_local signext i32 @foo1._v(
-// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo1.default(
-// CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo2._zbb(
-// CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo2._m(
-// CHECK-SAME: ) #[[ATTR3:[0-9]+]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo2.default(
-// CHECK-SAME: ) #[[ATTR1]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo3._c_zbb(
-// CHECK-SAME: ) #[[ATTR4:[0-9]+]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo3._m(
-// CHECK-SAME: ) #[[ATTR3]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo3.default(
-// CHECK-SAME: ) #[[ATTR1]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo4._zba(
-// CHECK-SAME: ) #[[ATTR5:[0-9]+]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo4._zbb(
-// CHECK-SAME: ) #[[ATTR2]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo4._zba_zbb(
-// CHECK-SAME: ) #[[ATTR6:[0-9]+]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo4.default(
-// CHECK-SAME: ) #[[ATTR1]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo5._zba(
-// CHECK-SAME: ) #[[ATTR5]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo5._zba_zbb(
-// CHECK-SAME: ) #[[ATTR6]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo5._zbb(
-// CHECK-SAME: ) #[[ATTR2]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo5.default(
-// CHECK-SAME: ) #[[ATTR1]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo6._zba(
-// CHECK-SAME: ) #[[ATTR5]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo6._zbb(
-// CHECK-SAME: ) #[[ATTR2]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo6._zba_zbb(
-// CHECK-SAME: ) #[[ATTR6]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo6.default(
-// CHECK-SAME: ) #[[ATTR1]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo7._zba(
-// CHECK-SAME: ) #[[ATTR5]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo7._zbb(
-// CHECK-SAME: ) #[[ATTR2]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo7._zba_zbb(
-// CHECK-SAME: ) #[[ATTR6]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo7.default(
-// CHECK-SAME: ) #[[ATTR1]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo8._zba(
-// CHECK-SAME: ) #[[ATTR5]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo8._zbb(
-// CHECK-SAME: ) #[[ATTR2]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo8._zba_zbb(
-// CHECK-SAME: ) #[[ATTR6]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @foo8.default(
-// CHECK-SAME: ) #[[ATTR1]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local signext i32 @bar(
-// CHECK-SAME: ) #[[ATTR1]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[CALL:%.*]] = call signext i32 @foo1()
-// CHECK-NEXT: [[CALL1:%.*]] = call signext i32 @foo2()
-// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
-// CHECK-NEXT: [[CALL2:%.*]] = call signext i32 @foo3()
-// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]]
-// CHECK-NEXT: [[CALL4:%.*]] = call signext i32 @foo4()
-// CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]]
-// CHECK-NEXT: [[CALL6:%.*]] = call signext i32 @foo5()
-// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]]
-// CHECK-NEXT: [[CALL8:%.*]] = call signext i32 @foo6()
-// CHECK-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CALL8]]
-// CHECK-NEXT: [[CALL10:%.*]] = call signext i32 @foo7()
-// CHECK-NEXT: [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]]
-// CHECK-NEXT: [[CALL12:%.*]] = call signext i32 @foo8()
-// CHECK-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CALL12]]
-// CHECK-NEXT: ret i32 [[ADD13]]
-//
-//
-// CHECK-LABEL: define weak_odr ptr @foo1.resolver() comdat {
-// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 2097152
-// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 2097152
-// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @foo1._v
-// CHECK: resolver_else:
-// CHECK-NEXT: ret ptr @foo1.default
-//
-//
-// CHECK-LABEL: define weak_odr ptr @foo2.resolver() comdat {
-// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435456
-// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435456
-// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @foo2._zbb
-// CHECK: resolver_else:
-// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 4096
-// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 4096
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
-// CHECK: resolver_return1:
-// CHECK-NEXT: ret ptr @foo2._m
-// CHECK: resolver_else2:
-// CHECK-NEXT: ret ptr @foo2.default
-//
-//
-// CHECK-LABEL: define weak_odr ptr @foo3.resolver() comdat {
-// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435460
-// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435460
-// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @foo3._c_zbb
-// CHECK: resolver_else:
-// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 4096
-// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 4096
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
-// CHECK: resolver_return1:
-// CHECK-NEXT: ret ptr @foo3._m
-// CHECK: resolver_else2:
-// CHECK-NEXT: ret ptr @foo3.default
-//
-//
-// CHECK-LABEL: define weak_odr ptr @foo4.resolver() comdat {
-// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 134217728
-// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 134217728
-// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @foo4._zba
-// CHECK: resolver_else:
-// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 268435456
-// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 268435456
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
-// CHECK: resolver_return1:
-// CHECK-NEXT: ret ptr @foo4._zbb
-// CHECK: resolver_else2:
-// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 402653184
-// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 402653184
-// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
-// CHECK: resolver_return3:
-// CHECK-NEXT: ret ptr @foo4._zba_zbb
-// CHECK: resolver_else4:
-// CHECK-NEXT: ret ptr @foo4.default
-//
-//
-// CHECK-LABEL: define weak_odr ptr @foo5.resolver() comdat {
-// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 134217728
-// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 134217728
-// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @foo5._zba
-// CHECK: resolver_else:
-// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 402653184
-// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 402653184
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
-// CHECK: resolver_return1:
-// CHECK-NEXT: ret ptr @foo5._zba_zbb
-// CHECK: resolver_else2:
-// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 268435456
-// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 268435456
-// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
-// CHECK: resolver_return3:
-// CHECK-NEXT: ret ptr @foo5._zbb
-// CHECK: resolver_else4:
-// CHECK-NEXT: ret ptr @foo5.default
-//
-//
-// CHECK-LABEL: define weak_odr ptr @foo6.resolver() comdat {
-// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184
-// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184
-// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @foo6._zba_zbb
-// CHECK: resolver_else:
-// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 134217728
-// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
-// CHECK: resolver_return1:
-// CHECK-NEXT: ret ptr @foo6._zba
-// CHECK: resolver_else2:
-// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 268435456
-// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 268435456
-// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
-// CHECK: resolver_return3:
-// CHECK-NEXT: ret ptr @foo6._zbb
-// CHECK: resolver_else4:
-// CHECK-NEXT: ret ptr @foo6.default
-//
-//
-// CHECK-LABEL: define weak_odr ptr @foo7.resolver() comdat {
-// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184
-// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184
-// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @foo7._zba_zbb
-// CHECK: resolver_else:
-// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 268435456
-// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 268435456
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
-// CHECK: resolver_return1:
-// CHECK-NEXT: ret ptr @foo7._zbb
-// CHECK: resolver_else2:
-// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 134217728
-// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 134217728
-// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
-// CHECK: resolver_return3:
-// CHECK-NEXT: ret ptr @foo7._zba
-// CHECK: resolver_else4:
-// CHECK-NEXT: ret ptr @foo7.default
-//
-//
-// CHECK-LABEL: define weak_odr ptr @foo8.resolver() comdat {
-// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184
-// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184
-// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @foo8._zba_zbb
-// CHECK: resolver_else:
-// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 134217728
-// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
-// CHECK: resolver_return1:
-// CHECK-NEXT: ret ptr @foo8._zba
-// CHECK: resolver_else2:
-// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 268435456
-// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 268435456
-// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
-// CHECK: resolver_return3:
-// CHECK-NEXT: ret ptr @foo8._zbb
-// CHECK: resolver_else4:
-// CHECK-NEXT: ret ptr @foo8.default
-//
-//.
-// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
-// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" }
-// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zbb" }
-// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" }
-// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+c,+i,+zbb" }
-// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zba" }
-// CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zba,+zbb" }
-//.
-// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
-// CHECK: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"lp64"}
-// CHECK: [[META2:![0-9]+]] = !{i32 6, !"riscv-isa", [[META3:![0-9]+]]}
-// CHECK: [[META3]] = !{!"rv64i2p1"}
-// CHECK: [[META4:![0-9]+]] = !{i32 8, !"SmallDataLimit", i32 0}
-// CHECK: [[META5:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
-//.
diff --git a/clang/test/CodeGenCXX/attr-target-version-riscv.cpp b/clang/test/CodeGenCXX/attr-target-version-riscv.cpp
deleted file mode 100644
index 9078f6541b3dcb..00000000000000
--- a/clang/test/CodeGenCXX/attr-target-version-riscv.cpp
+++ /dev/null
@@ -1,432 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --include-generated-funcs --version 4
-// RUN: %clang_cc1 -std=c++11 -triple riscv64-linux-gnu -target-feature +i -target-feature +m -emit-llvm %s -o - | FileCheck %s
-
-__attribute__((target_version("arch=+v"))) int foo1(void) { return 1; }
-__attribute__((target_version("default"))) int foo1(void) { return 1; }
-
-__attribute__((target_version("arch=+zbb"))) int foo2(void) { return 1; }
-__attribute__((target_version("arch=+m"))) int foo2(void) { return 1; }
-__attribute__((target_version("default"))) int foo2(void) { return 1; }
-
-__attribute__((target_version("arch=+zbb,+c"))) int foo3(void) { return 1; }
-__attribute__((target_version("arch=+m"))) int foo3(void) { return 1; }
-__attribute__((target_version("default"))) int foo3(void) { return 1; }
-
-__attribute__((target_version("arch=+zba"))) int foo4(void) { return 1; }
-__attribute__((target_version("arch=+zbb"))) int foo4(void) { return 1; }
-__attribute__((target_version("arch=+zbb,+zba"))) int foo4(void) { return 1; }
-__attribute__((target_version("default"))) int foo4(void) { return 1; }
-
-__attribute__((target_version("arch=+zba"))) int foo5(void) { return 1; }
-__attribute__((target_version("arch=+zbb,+zba"))) int foo5(void) { return 1; }
-__attribute__((target_version("arch=+zbb"))) int foo5(void) { return 1; }
-__attribute__((target_version("default"))) int foo5(void) { return 1; }
-
-__attribute__((target_version("arch=+zba"))) int foo6(void) { return 1; }
-__attribute__((target_version("arch=+zbb"))) int foo6(void) { return 1; }
-__attribute__((target_version("arch=+zbb,+zba;priority=10"))) int foo6(void) { return 1; }
-__attribute__((target_version("default"))) int foo6(void) { return 1; }
-
-__attribute__((target_version("priority=8;arch=+zba"))) int foo7(void) { return 1; }
-__attribute__((target_version("arch=+zbb;priority=9"))) int foo7(void) { return 1; }
-__attribute__((target_version("arch=+zbb,+zba;priority=10"))) int foo7(void) { return 1; }
-__attribute__((target_version("default"))) int foo7(void) { return 1; }
-
-__attribute__((target_version("priority=-1;arch=+zba"))) int foo8(void) { return 1; }
-__attribute__((target_version("arch=+zbb;priority=-2"))) int foo8(void) { return 1; }
-__attribute__((target_version("arch=+zbb,+zba;priority=3"))) int foo8(void) { return 1; }
-__attribute__((target_version("default"))) int foo8(void) { return 1; }
-
-int bar() { return foo1() + foo2() + foo3(); }
-//.
-// CHECK: @__riscv_feature_bits = external dso_local global { i32, [2 x i64] }
-// CHECK: @_Z4foo1v = weak_odr ifunc i32 (), ptr @_Z4foo1v.resolver
-// CHECK: @_Z4foo2v = weak_odr ifunc i32 (), ptr @_Z4foo2v.resolver
-// CHECK: @_Z4foo3v = weak_odr ifunc i32 (), ptr @_Z4foo3v.resolver
-// CHECK: @_Z4foo4v = weak_odr ifunc i32 (), ptr @_Z4foo4v.resolver
-// CHECK: @_Z4foo5v = weak_odr ifunc i32 (), ptr @_Z4foo5v.resolver
-// CHECK: @_Z4foo6v = weak_odr ifunc i32 (), ptr @_Z4foo6v.resolver
-// CHECK: @_Z4foo7v = weak_odr ifunc i32 (), ptr @_Z4foo7v.resolver
-// CHECK: @_Z4foo8v = weak_odr ifunc i32 (), ptr @_Z4foo8v.resolver
-//.
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo1v._v(
-// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo1v.default(
-// CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v._zbb(
-// CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v._m(
-// CHECK-SAME: ) #[[ATTR1]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v.default(
-// CHECK-SAME: ) #[[ATTR1]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v._c_zbb(
-// CHECK-SAME: ) #[[ATTR3:[0-9]+]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v._m(
-// CHECK-SAME: ) #[[ATTR1]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v.default(
-// CHECK-SAME: ) #[[ATTR1]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v._zba(
-// CHECK-SAME: ) #[[ATTR4:[0-9]+]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v._zbb(
-// CHECK-SAME: ) #[[ATTR2]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v._zba_zbb(
-// CHECK-SAME: ) #[[ATTR5:[0-9]+]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v.default(
-// CHECK-SAME: ) #[[ATTR1]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v._zba(
-// CHECK-SAME: ) #[[ATTR4]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v._zba_zbb(
-// CHECK-SAME: ) #[[ATTR5]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v._zbb(
-// CHECK-SAME: ) #[[ATTR2]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v.default(
-// CHECK-SAME: ) #[[ATTR1]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v._zba(
-// CHECK-SAME: ) #[[ATTR4]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v._zbb(
-// CHECK-SAME: ) #[[ATTR2]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v._zba_zbb(
-// CHECK-SAME: ) #[[ATTR5]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v.default(
-// CHECK-SAME: ) #[[ATTR1]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zba(
-// CHECK-SAME: ) #[[ATTR4]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zbb(
-// CHECK-SAME: ) #[[ATTR2]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v._zba_zbb(
-// CHECK-SAME: ) #[[ATTR5]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo7v.default(
-// CHECK-SAME: ) #[[ATTR1]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v._zba(
-// CHECK-SAME: ) #[[ATTR4]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v._zbb(
-// CHECK-SAME: ) #[[ATTR2]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v._zba_zbb(
-// CHECK-SAME: ) #[[ATTR5]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo8v.default(
-// CHECK-SAME: ) #[[ATTR1]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: ret i32 1
-//
-//
-// CHECK-LABEL: define dso_local noundef signext i32 @_Z3barv(
-// CHECK-SAME: ) #[[ATTR1]] {
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z4foo1v()
-// CHECK-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_Z4foo2v()
-// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
-// CHECK-NEXT: [[CALL2:%.*]] = call noundef signext i32 @_Z4foo3v()
-// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]]
-// CHECK-NEXT: ret i32 [[ADD3]]
-//
-//
-// CHECK-LABEL: define weak_odr ptr @_Z4foo1v.resolver() comdat {
-// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 2097152
-// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 2097152
-// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @_Z4foo1v._v
-// CHECK: resolver_else:
-// CHECK-NEXT: ret ptr @_Z4foo1v.default
-//
-//
-// CHECK-LABEL: define weak_odr ptr @_Z4foo2v.resolver() comdat {
-// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435456
-// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435456
-// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @_Z4foo2v._zbb
-// CHECK: resolver_else:
-// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 4096
-// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 4096
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
-// CHECK: resolver_return1:
-// CHECK-NEXT: ret ptr @_Z4foo2v._m
-// CHECK: resolver_else2:
-// CHECK-NEXT: ret ptr @_Z4foo2v.default
-//
-//
-// CHECK-LABEL: define weak_odr ptr @_Z4foo3v.resolver() comdat {
-// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435460
-// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435460
-// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @_Z4foo3v._c_zbb
-// CHECK: resolver_else:
-// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 4096
-// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 4096
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
-// CHECK: resolver_return1:
-// CHECK-NEXT: ret ptr @_Z4foo3v._m
-// CHECK: resolver_else2:
-// CHECK-NEXT: ret ptr @_Z4foo3v.default
-//
-//
-// CHECK-LABEL: define weak_odr ptr @_Z4foo4v.resolver() comdat {
-// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 134217728
-// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 134217728
-// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @_Z4foo4v._zba
-// CHECK: resolver_else:
-// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 268435456
-// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 268435456
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
-// CHECK: resolver_return1:
-// CHECK-NEXT: ret ptr @_Z4foo4v._zbb
-// CHECK: resolver_else2:
-// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 402653184
-// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 402653184
-// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
-// CHECK: resolver_return3:
-// CHECK-NEXT: ret ptr @_Z4foo4v._zba_zbb
-// CHECK: resolver_else4:
-// CHECK-NEXT: ret ptr @_Z4foo4v.default
-//
-//
-// CHECK-LABEL: define weak_odr ptr @_Z4foo5v.resolver() comdat {
-// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 134217728
-// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 134217728
-// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @_Z4foo5v._zba
-// CHECK: resolver_else:
-// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 402653184
-// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 402653184
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
-// CHECK: resolver_return1:
-// CHECK-NEXT: ret ptr @_Z4foo5v._zba_zbb
-// CHECK: resolver_else2:
-// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 268435456
-// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 268435456
-// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
-// CHECK: resolver_return3:
-// CHECK-NEXT: ret ptr @_Z4foo5v._zbb
-// CHECK: resolver_else4:
-// CHECK-NEXT: ret ptr @_Z4foo5v.default
-//
-//
-// CHECK-LABEL: define weak_odr ptr @_Z4foo6v.resolver() comdat {
-// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184
-// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184
-// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @_Z4foo6v._zba_zbb
-// CHECK: resolver_else:
-// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 134217728
-// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
-// CHECK: resolver_return1:
-// CHECK-NEXT: ret ptr @_Z4foo6v._zba
-// CHECK: resolver_else2:
-// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 268435456
-// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 268435456
-// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
-// CHECK: resolver_return3:
-// CHECK-NEXT: ret ptr @_Z4foo6v._zbb
-// CHECK: resolver_else4:
-// CHECK-NEXT: ret ptr @_Z4foo6v.default
-//
-//
-// CHECK-LABEL: define weak_odr ptr @_Z4foo7v.resolver() comdat {
-// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184
-// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184
-// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @_Z4foo7v._zba_zbb
-// CHECK: resolver_else:
-// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 268435456
-// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 268435456
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
-// CHECK: resolver_return1:
-// CHECK-NEXT: ret ptr @_Z4foo7v._zbb
-// CHECK: resolver_else2:
-// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 134217728
-// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 134217728
-// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
-// CHECK: resolver_return3:
-// CHECK-NEXT: ret ptr @_Z4foo7v._zba
-// CHECK: resolver_else4:
-// CHECK-NEXT: ret ptr @_Z4foo7v.default
-//
-//
-// CHECK-LABEL: define weak_odr ptr @_Z4foo8v.resolver() comdat {
-// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_feature_bits(ptr null)
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 402653184
-// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184
-// CHECK-NEXT: br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @_Z4foo8v._zba_zbb
-// CHECK: resolver_else:
-// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], 134217728
-// CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
-// CHECK: resolver_return1:
-// CHECK-NEXT: ret ptr @_Z4foo8v._zba
-// CHECK: resolver_else2:
-// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], 268435456
-// CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 268435456
-// CHECK-NEXT: br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
-// CHECK: resolver_return3:
-// CHECK-NEXT: ret ptr @_Z4foo8v._zbb
-// CHECK: resolver_else4:
-// CHECK-NEXT: ret ptr @_Z4foo8v.default
-//
-//.
-// CHECK: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+m,+v,+zicsr,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
-// CHECK: attributes #[[ATTR1]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" }
-// CHECK: attributes #[[ATTR2]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zbb,+zmmul" }
-// CHECK: attributes #[[ATTR3]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+c,+i,+m,+zbb,+zmmul" }
-// CHECK: attributes #[[ATTR4]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zba,+zmmul" }
-// CHECK: attributes #[[ATTR5]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zba,+zbb,+zmmul" }
-//.
-// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
-// CHECK: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"lp64"}
-// CHECK: [[META2:![0-9]+]] = !{i32 6, !"riscv-isa", [[META3:![0-9]+]]}
-// CHECK: [[META3]] = !{!"rv64i2p1_m2p0_zmmul1p0"}
-// CHECK: [[META4:![0-9]+]] = !{i32 8, !"SmallDataLimit", i32 0}
-// CHECK: [[META5:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
-//.
diff --git a/clang/test/SemaCXX/attr-target-version-riscv.cpp b/clang/test/SemaCXX/attr-target-version-riscv.cpp
deleted file mode 100644
index 785a3c6abafe8c..00000000000000
--- a/clang/test/SemaCXX/attr-target-version-riscv.cpp
+++ /dev/null
@@ -1,113 +0,0 @@
-// RUN: %clang_cc1 -triple riscv64-linux-gnu -fsyntax-only -verify -fexceptions -fcxx-exceptions %s -std=c++14
-
-// expected-warning at +2 {{unsupported 'arch=rv64gcv' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-// expected-note at +1 {{previous definition is here}}
-__attribute__((target_version("arch=rv64gcv"))) int fullArchString(void) { return 2; }
-// expected-error at +2 {{redefinition of 'fullArchString'}}
-// expected-warning at +1 {{unsupported 'arch=default' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-__attribute__((target_version("arch=default"))) int fullArchString(void) { return 2; }
-
-// expected-warning at +2 {{unsupported 'mcpu=sifive-u74' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-// expected-note at +1 {{previous definition is here}}
-__attribute__((target_version("mcpu=sifive-u74"))) int mcpu(void) { return 2; }
-// expected-error at +1 {{redefinition of 'mcpu'}}
-__attribute__((target_version("default"))) int mcpu(void) { return 2; }
-
-// expected-warning at +2 {{unsupported 'mtune=sifive-u74' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-// expected-note at +1 {{previous definition is here}}
-__attribute__((target_version("mtune=sifive-u74"))) int mtune(void) { return 2; }
-// expected-error at +1 {{redefinition of 'mtune'}}
-__attribute__((target_version("default"))) int mtune(void) { return 2; }
-
-// expected-warning at +2 {{unsupported '' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-// expected-note at +1 {{previous definition is here}}
-__attribute__((target_version(""))) int emptyVersion(void) { return 2; }
-// expected-error at +1 {{redefinition of 'emptyVersion'}}
-__attribute__((target_version("default"))) int emptyVersion(void) { return 2; }
-
-// expected-note at +1 {{previous definition is here}}
-__attribute__((target_version("arch=+c"))) int dupVersion(void) { return 2; }
-// expected-error at +1 {{redefinition of 'dupVersion'}}
-__attribute__((target_version("arch=+c"))) int dupVersion(void) { return 2; }
-__attribute__((target_version("default"))) int dupVersion(void) { return 2; }
-
-// expected-warning at +2 {{unsupported 'arch=+zicsr' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-// expected-note at +1 {{previous definition is here}}
-__attribute__((target_version("arch=+zicsr"))) int UnsupportBitMaskExt(void) { return 2; }
-// expected-error at +1 {{redefinition of 'UnsupportBitMaskExt'}}
-__attribute__((target_version("default"))) int UnsupportBitMaskExt(void) { return 2; }
-
-// expected-warning at +2 {{unsupported 'NotADigit' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-// expected-note at +1 {{previous definition is here}}
-__attribute__((target_version("arch=+c;priority=NotADigit"))) int UnsupportPriority(void) { return 2; }
-// expected-error at +1 {{redefinition of 'UnsupportPriority'}}
-__attribute__((target_version("default"))) int UnsupportPriority(void) { return 2;}
-
-// expected-warning at +1 {{unsupported 'default;priority=2' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-__attribute__((target_version("default;priority=2"))) int UnsupportDefaultPriority(void) { return 2; }
-
-// expected-warning at +2 {{unsupported 'arch=+c,zbb' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-// expected-note at +1 {{previous definition is here}}
-__attribute__((target_version("arch=+c,zbb"))) int WithoutAddSign(void) { return 2;}
-// expected-error at +1 {{redefinition of 'WithoutAddSign'}}
-__attribute__((target_version("default"))) int WithoutAddSign(void) { return 2; }
-
-// expected-warning at +2 {{unsupported 'arch=+c;default' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-// expected-note at +1 {{previous definition is here}}
-__attribute__((target_version("arch=+c;default"))) int DefaultInVersion(void) { return 2;}
-// expected-error at +1 {{redefinition of 'DefaultInVersion'}}
-__attribute__((target_version("default"))) int DefaultInVersion(void) { return 2; }
-
-// expected-warning at +2 {{unsupported '' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-// expected-note at +1 {{previous definition is here}}
-__attribute__((target_version("arch=+c;"))) int EmptyVersionAfterSemiColon(void) { return 2;}
-// expected-error at +1 {{redefinition of 'EmptyVersionAfterSemiColon'}}
-__attribute__((target_version("default"))) int EmptyVersionAfterSemiColon(void) { return 2; }
-
-// expected-warning at +2 {{unsupported 'arch=+c;arch=+f' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-// expected-note at +1 {{previous definition is here}}
-__attribute__((target_version("arch=+c;arch=+f"))) int dupArch(void) { return 2; }
-// expected-error at +1 {{redefinition of 'dupArch'}}
-__attribute__((target_version("default"))) int dupArch(void) { return 2; }
-
-// expected-warning at +2 {{unsupported 'default;default' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-// expected-note at +1 {{previous definition is here}}
-__attribute__((target_version("default;default"))) int dupDefault(void) { return 2;}
-// expected-error at +1 {{redefinition of 'dupDefault'}}
-__attribute__((target_version("default"))) int dupDefault(void) { return 2; }
-
-// expected-warning at +2 {{unsupported 'priority=1;priority=2' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-// expected-note at +1 {{previous definition is here}}
-__attribute__((target_version("priority=1;priority=2"))) int dupPriority(void) { return 2; }
-// expected-error at +1 {{redefinition of 'dupPriority'}}
-__attribute__((target_version("default"))) int dupPriority(void) { return 2; }
-
-// expected-warning at +2 {{unsupported '=1' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-// expected-note at +1 {{previous definition is here}}
-__attribute__((target_version("=1"))) int invalidVerson1(void) { return 2; }
-// expected-error at +1 {{redefinition of 'invalidVerson1'}}
-__attribute__((target_version("default"))) int invalidVerson1(void) { return 2; }
-
-// expected-warning at +2 {{unsupported '=+v' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-// expected-note at +1 {{previous definition is here}}
-__attribute__((target_version("=+v"))) int invalidVerson2(void) { return 2; }
-// expected-error at +1 {{redefinition of 'invalidVerson2'}}
-__attribute__((target_version("default"))) int invalidVerson2(void) { return 2; }
-
-// expected-warning at +2 {{unsupported 'v' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-// expected-note at +1 {{previous definition is here}}
-__attribute__((target_version("v"))) int invalidVerson3(void) { return 2; }
-// expected-error at +1 {{redefinition of 'invalidVerson3'}}
-__attribute__((target_version("default"))) int invalidVerson3(void) { return 2; }
-
-// expected-warning at +2 {{unsupported '' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-// expected-note at +1 {{previous definition is here}}
-__attribute__((target_version(";"))) int invalidVerson4(void) { return 2; }
-// expected-error at +1 {{redefinition of 'invalidVerson4'}}
-__attribute__((target_version("default"))) int invalidVerson4(void) { return 2; }
-
-// expected-warning at +2 {{unsupported 'priority=1' in the 'target_version' attribute string; 'target_version' attribute ignored}}
-// expected-note at +1 {{previous definition is here}}
-__attribute__((target_version("priority=1"))) int prioriyWithoutArch(void) { return 2; }
-// expected-error at +1 {{redefinition of 'prioriyWithoutArch'}}
-__attribute__((target_version("default"))) int prioriyWithoutArch(void) { return 2; }
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