[llvm-branch-commits] [RISCV] Set DisableLatencyHeuristic to true (PR #115858)

[Pengcheng Wang via llvm-branch-commits]

wangpc-pp wrote:

Thanks for evaluating this! The data is very helpful! @michaelmaitland 

> Given @michaelmaitland's data, @wangpc-pp the burden shifts to you to clearly justify which cases this is profitable and figure out how to selectively enable only in profitable cases. I agree with @michaelmaitland's conclusion that this should not move forward otherwise.

I don't have other data other than the spill/reload data above. I don't know how to dynamically determine if a SchedDAG region will benefit from disabling it because we can only know `NumRegionInstrs` (we may change the function signature and pass DAG directly in the future so that we can analyse the region). AArch64 is the only target will disable it and almost all Apple's CPUs have this feature on (don't know if it is profitable or they are just some inertial copies when defining new processor).

Again, if the conclusion is that we shouldn't make it true by default, I can make it a tune feature. All I want is making scheduling infrastructure easy to tune for downstreams. :-)

https://github.com/llvm/llvm-project/pull/115858