[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)
Pengcheng Wang via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Nov 22 04:03:14 PST 2024
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/116231
>From 9686a2c5c5276289e72d9098f497a9f246a1c457 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Thu, 14 Nov 2024 22:06:45 +0800
Subject: [PATCH 1/4] Remove stale CHECKs
Created using spr 1.3.6-beta.1
---
clang/test/CodeGen/builtin-cpu-is.c | 20 --------------------
1 file changed, 20 deletions(-)
diff --git a/clang/test/CodeGen/builtin-cpu-is.c b/clang/test/CodeGen/builtin-cpu-is.c
index e4a2071cf46795..b8dd97eeacebcf 100644
--- a/clang/test/CodeGen/builtin-cpu-is.c
+++ b/clang/test/CodeGen/builtin-cpu-is.c
@@ -7,8 +7,6 @@
// global, the bit grab, and the icmp correct.
extern void a(const char *);
-// CHECK: @__cpu_model = external dso_local global { i32, i32, i32, [1 x i32] }
-
// CHECK-X86-LABEL: define dso_local void @intel(
// CHECK-X86-SAME: ) #[[ATTR0:[0-9]+]] {
// CHECK-X86-NEXT: [[ENTRY:.*:]]
@@ -24,9 +22,6 @@ extern void a(const char *);
void intel(void) {
if (__builtin_cpu_is("intel"))
a("intel");
-
- // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr @__cpu_model
- // CHECK: = icmp eq i32 [[LOAD]], 1
}
// CHECK-X86-LABEL: define dso_local void @amd(
@@ -44,9 +39,6 @@ void intel(void) {
void amd(void) {
if (__builtin_cpu_is("amd"))
a("amd");
-
- // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr @__cpu_model
- // CHECK: = icmp eq i32 [[LOAD]], 2
}
// CHECK-X86-LABEL: define dso_local void @atom(
@@ -64,9 +56,6 @@ void amd(void) {
void atom(void) {
if (__builtin_cpu_is("atom"))
a("atom");
-
- // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32, i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 1)
- // CHECK: = icmp eq i32 [[LOAD]], 1
}
// CHECK-X86-LABEL: define dso_local void @amdfam10h(
@@ -84,9 +73,6 @@ void atom(void) {
void amdfam10h(void) {
if (__builtin_cpu_is("amdfam10h"))
a("amdfam10h");
-
- // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32, i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 1)
- // CHECK: = icmp eq i32 [[LOAD]], 4
}
// CHECK-X86-LABEL: define dso_local void @barcelona(
@@ -104,9 +90,6 @@ void amdfam10h(void) {
void barcelona(void) {
if (__builtin_cpu_is("barcelona"))
a("barcelona");
-
- // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32, i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 2)
- // CHECK: = icmp eq i32 [[LOAD]], 4
}
// CHECK-X86-LABEL: define dso_local void @nehalem(
@@ -124,9 +107,6 @@ void barcelona(void) {
void nehalem(void) {
if (__builtin_cpu_is("nehalem"))
a("nehalem");
-
- // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32, i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 2)
- // CHECK: = icmp eq i32 [[LOAD]], 1
}
#endif
>From 2bb2d5079b5bf98ba9f87e082ca3e67ab70068aa Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Thu, 14 Nov 2024 22:12:36 +0800
Subject: [PATCH 2/4] Simplify test
Created using spr 1.3.6-beta.1
---
clang/test/CodeGen/builtin-cpu-is.c | 25 ++++++-------------------
1 file changed, 6 insertions(+), 19 deletions(-)
diff --git a/clang/test/CodeGen/builtin-cpu-is.c b/clang/test/CodeGen/builtin-cpu-is.c
index b8dd97eeacebcf..8e78213a7cfcfb 100644
--- a/clang/test/CodeGen/builtin-cpu-is.c
+++ b/clang/test/CodeGen/builtin-cpu-is.c
@@ -111,12 +111,9 @@ void nehalem(void) {
#endif
#ifdef __riscv
-// CHECK-RV64-LABEL: define dso_local signext i32 @test_riscv(
-// CHECK-RV64-SAME: i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-LABEL: define dso_local signext i32 @test_cpu_is_veyron_v1(
+// CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
-// CHECK-RV64-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
-// CHECK-RV64-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK-RV64-NEXT: [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 4
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1567
// CHECK-RV64-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 1), align 8
@@ -125,20 +122,10 @@ void nehalem(void) {
// CHECK-RV64-NEXT: [[TMP5:%.*]] = load i64, ptr getelementptr inbounds ({ i32, i64, i64 }, ptr @__riscv_cpu_model, i32 0, i32 2), align 8
// CHECK-RV64-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 273
// CHECK-RV64-NEXT: [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]
-// CHECK-RV64-NEXT: br i1 [[TMP7]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
-// CHECK-RV64: [[IF_THEN]]:
-// CHECK-RV64-NEXT: store i32 3, ptr [[RETVAL]], align 4
-// CHECK-RV64-NEXT: br label %[[RETURN:.*]]
-// CHECK-RV64: [[IF_END]]:
-// CHECK-RV64-NEXT: store i32 0, ptr [[RETVAL]], align 4
-// CHECK-RV64-NEXT: br label %[[RETURN]]
-// CHECK-RV64: [[RETURN]]:
-// CHECK-RV64-NEXT: [[TMP8:%.*]] = load i32, ptr [[RETVAL]], align 4
-// CHECK-RV64-NEXT: ret i32 [[TMP8]]
+// CHECK-RV64-NEXT: [[CONV:%.*]] = zext i1 [[TMP7]] to i32
+// CHECK-RV64-NEXT: ret i32 [[CONV]]
//
-int test_riscv(int a) {
- if (__builtin_cpu_is("veyron-v1"))
- return 3;
- return 0;
+int test_cpu_is_veyron_v1() {
+ return __builtin_cpu_is("veyron-v1");
}
#endif
>From 8afe59fad4b67649d464b1d397f7a8bd0d0e9bcf Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Thu, 14 Nov 2024 22:17:59 +0800
Subject: [PATCH 3/4] marchid and mimplid can be 0
Created using spr 1.3.6-beta.1
---
llvm/lib/TargetParser/RISCVTargetParser.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index d62e1ba25cd94d..eaf17431b49984 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -73,7 +73,7 @@ bool hasFastVectorUnalignedAccess(StringRef CPU) {
bool hasValidCPUModel(StringRef CPU) {
const CPUInfo *Info = getCPUInfoByName(CPU);
- return Info && Info->MVendorID && Info->MArchID && Info->MImpID;
+ return Info && Info->MVendorID;
}
uint32_t getVendorID(StringRef CPU) {
>From 0e8827873293309615f66e376b955c913f7c5861 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Thu, 14 Nov 2024 22:19:26 +0800
Subject: [PATCH 4/4] Revert last change
Created using spr 1.3.6-beta.1
---
llvm/lib/TargetParser/RISCVTargetParser.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index eaf17431b49984..d62e1ba25cd94d 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -73,7 +73,7 @@ bool hasFastVectorUnalignedAccess(StringRef CPU) {
bool hasValidCPUModel(StringRef CPU) {
const CPUInfo *Info = getCPUInfoByName(CPU);
- return Info && Info->MVendorID;
+ return Info && Info->MVendorID && Info->MArchID && Info->MImpID;
}
uint32_t getVendorID(StringRef CPU) {
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