[llvm-branch-commits] [RISCV] Set DisableLatencyHeuristic to true (PR #115858)

[Min-Yih Hsu via llvm-branch-commits]

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@@ -727,27 +728,49 @@ define void @buildvec_seq_v4i16_v2i32(ptr %x) {
 }
 
 define void @buildvec_vid_step1o2_v4i32(ptr %z0, ptr %z1, ptr %z2, ptr %z3, ptr %z4, ptr %z5, ptr %z6) {
-; CHECK-LABEL: buildvec_vid_step1o2_v4i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT:    vmv.v.i v8, 1
-; CHECK-NEXT:    vmv.s.x v9, zero
-; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
-; CHECK-NEXT:    vslideup.vi v8, v9, 1
-; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT:    vid.v v9
-; CHECK-NEXT:    vsrl.vi v9, v9, 1
-; CHECK-NEXT:    vse32.v v9, (a0)
-; CHECK-NEXT:    vse32.v v9, (a1)
-; CHECK-NEXT:    vse32.v v9, (a2)
-; CHECK-NEXT:    vse32.v v9, (a3)
-; CHECK-NEXT:    vse32.v v9, (a4)
-; CHECK-NEXT:    vmv.v.i v9, 0
-; CHECK-NEXT:    li a0, 1
-; CHECK-NEXT:    vslide1down.vx v9, v9, a0
-; CHECK-NEXT:    vse32.v v8, (a5)
-; CHECK-NEXT:    vse32.v v9, (a6)
-; CHECK-NEXT:    ret
+; RV32-LABEL: buildvec_vid_step1o2_v4i32:
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mshockwave wrote:

why do we have different scheduling between RV32 and RV64?

https://github.com/llvm/llvm-project/pull/115858