[llvm-branch-commits] [mlir] [mlir][Transforms] Add 1:N `matchAndRewrite` overload (PR #116470)

[Markus Böck via llvm-branch-commits]

================
@@ -1145,15 +1170,32 @@ LogicalResult ConversionPatternRewriterImpl::remapValues(
       return failure();
     }
 
+    // If a type is converted to 0 types, there is nothing to do.
+    if (legalTypes.empty()) {
+      remapped.push_back({});
+      continue;
+    }
+
     if (legalTypes.size() != 1) {
-      // TODO: Parts of the dialect conversion infrastructure do not support
-      // 1->N type conversions yet. Therefore, if a type is converted to 0 or
-      // multiple types, the only thing that we can do for now is passing
-      // through the most recently mapped value. Fixing this requires
-      // improvements to the `ConversionValueMapping` (to be able to store 1:N
-      // mappings) and to the `ConversionPattern` adaptor handling (to be able
-      // to pass multiple remapped values for a single operand to the adaptor).
-      remapped.push_back(mapping.lookupOrDefault(operand));
+      // TODO: This is a 1:N conversion. The conversion value mapping does not
+      // support such conversions yet. It stores the result of an argument
+      // materialization (i.e., a conversion back into a single SSA value)
+      // instead. Unpack such "workaround" materializations and hand the
+      // original replacement values to the adaptor.
+      Value repl = mapping.lookupOrDefault(operand);
+      SmallVector<Value> unpacked = unpackNTo1Materialization(repl);
+      if (TypeRange(unpacked) == legalTypes) {
+        remapped.push_back(unpacked);
----------------
zero9178 wrote:

```suggestion
        remapped.push_back(std::move(unpacked));
```

https://github.com/llvm/llvm-project/pull/116470