[llvm-branch-commits] [RISCV] Enable ShouldTrackLaneMasks when having vector instructions (PR #115843)

[Pengcheng Wang via llvm-branch-commits]

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/115843

This can help to improve the register pressure for LMUL>1 cases.