[llvm-branch-commits] [clang] [clang-tools-extra] [compiler-rt] [libcxx] [lld] [lldb] [llvm] [mlir][IR][NFC] `PostDominanceInfo`: Mark all functions as `const` (PR #115597)
Matthias Springer via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Sun Nov 10 18:34:18 PST 2024
https://github.com/matthias-springer updated https://github.com/llvm/llvm-project/pull/115597
>From e1495283cf74590fbdeb6d46ad815b4d10b1902f Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb at igalia.com>
Date: Sun, 10 Nov 2024 07:18:05 +0000
Subject: [PATCH 01/31] [RISCV] Use the 'B' extension in RISC-V profile
definitions (#113942)
RVA22 has retroactively been defined as including 'B' (as it's a
shorthand for Zba+Zbb+Zbs, which were previously explicitly enumerated)
and RV{A,B,M}23 are defined featuring B. We don't currently infer B
whenever Zba+Zbb+Zbs are present due to concerns about compatibility
with external assemblers such as gas.
We don't believe that adding B to RVA22 will cause issues for users who
(for instance) build with clang and assemble with binutils as looking at
the binutils commit history:
zic64b support was only committed in
25f05199bb7e35820c23e802424484accb7936b1 in July 2024
B support was committed in c144f638337944101131d9fe6de4ab908f6d4c2d in
May 2024
So given we emit zic64b anyway (as it has always been in the RVA22
spec), no binutils that would have previously successfully assembled our
rva22u64 output should fail due to the addition of 'B'.
---
clang/test/Driver/riscv-profiles.c | 8 ++++++++
llvm/lib/Target/RISCV/RISCVProfiles.td | 12 +++---------
llvm/test/CodeGen/RISCV/attributes.ll | 14 +++++++-------
3 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c
index 67e09d0e69ebc3..c87ec5a27822c5 100644
--- a/clang/test/Driver/riscv-profiles.c
+++ b/clang/test/Driver/riscv-profiles.c
@@ -57,6 +57,7 @@
// RVA22U64: "-target-feature" "+f"
// RVA22U64: "-target-feature" "+d"
// RVA22U64: "-target-feature" "+c"
+// RVA22U64: "-target-feature" "+b"
// RVA22U64: "-target-feature" "+zic64b"
// RVA22U64: "-target-feature" "+zicbom"
// RVA22U64: "-target-feature" "+zicbop"
@@ -83,6 +84,7 @@
// RVA22S64: "-target-feature" "+f"
// RVA22S64: "-target-feature" "+d"
// RVA22S64: "-target-feature" "+c"
+// RVA22S64: "-target-feature" "+b"
// RVA22S64: "-target-feature" "+zic64b"
// RVA22S64: "-target-feature" "+zicbom"
// RVA22S64: "-target-feature" "+zicbop"
@@ -118,6 +120,7 @@
// RVA23U64: "-target-feature" "+f"
// RVA23U64: "-target-feature" "+d"
// RVA23U64: "-target-feature" "+c"
+// RVA23U64: "-target-feature" "+b"
// RVA23U64: "-target-feature" "+v"
// RVA23U64: "-target-feature" "+zic64b"
// RVA23U64: "-target-feature" "+zicbom"
@@ -156,6 +159,7 @@
// RVA23S64: "-target-feature" "+f"
// RVA23S64: "-target-feature" "+d"
// RVA23S64: "-target-feature" "+c"
+// RVA23S64: "-target-feature" "+b"
// RVA23S64: "-target-feature" "+v"
// RVA23S64: "-target-feature" "+h"
// RVA23S64: "-target-feature" "+zic64b"
@@ -217,6 +221,7 @@
// RVB23U64: "-target-feature" "+f"
// RVB23U64: "-target-feature" "+d"
// RVB23U64: "-target-feature" "+c"
+// RVB23U64: "-target-feature" "+b"
// RVB23U64: "-target-feature" "+zic64b"
// RVB23U64: "-target-feature" "+zicbom"
// RVB23U64: "-target-feature" "+zicbop"
@@ -249,6 +254,7 @@
// RVB23S64: "-target-feature" "+f"
// RVB23S64: "-target-feature" "+d"
// RVB23S64: "-target-feature" "+c"
+// RVB23S64: "-target-feature" "+b"
// RVB23S64: "-target-feature" "+zic64b"
// RVB23S64: "-target-feature" "+zicbom"
// RVB23S64: "-target-feature" "+zicbop"
@@ -290,6 +296,7 @@
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -march=rvm23u32 -menable-experimental-extensions \
// RUN: | FileCheck -check-prefix=RVM23U32 %s
// RVM23U32: "-target-feature" "+m"
+// RVM23U32: "-target-feature" "+b"
// RVM23U32: "-target-feature" "+zicbop"
// RVM23U32: "-target-feature" "+zicond"
// RVM23U32: "-target-feature" "+zicsr"
@@ -309,6 +316,7 @@
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+f"
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+d"
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+c"
+// PROFILE-WITH-ADDITIONAL: "-target-feature" "+b"
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zicbom"
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zicbop"
// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zicboz"
diff --git a/llvm/lib/Target/RISCV/RISCVProfiles.td b/llvm/lib/Target/RISCV/RISCVProfiles.td
index cbf2a2eddf38ed..bcb776e682aea7 100644
--- a/llvm/lib/Target/RISCV/RISCVProfiles.td
+++ b/llvm/lib/Target/RISCV/RISCVProfiles.td
@@ -45,9 +45,7 @@ defvar RVA22U64Features = !listconcat(RVA20U64BaseFeatures,
[FeatureStdExtZa64rs,
FeatureStdExtZihpm,
FeatureStdExtZihintpause,
- FeatureStdExtZba,
- FeatureStdExtZbb,
- FeatureStdExtZbs,
+ FeatureStdExtB,
FeatureStdExtZic64b,
FeatureStdExtZicbom,
FeatureStdExtZicbop,
@@ -92,9 +90,7 @@ defvar RVB23U64Features = !listconcat(RVA20U64BaseFeatures,
[FeatureStdExtZihpm,
FeatureStdExtZa64rs,
FeatureStdExtZihintpause,
- FeatureStdExtZba,
- FeatureStdExtZbb,
- FeatureStdExtZbs,
+ FeatureStdExtB,
FeatureStdExtZic64b,
FeatureStdExtZicbom,
FeatureStdExtZicbop,
@@ -128,9 +124,7 @@ defvar RVB23S64Features = !listconcat(RVB23U64Features,
defvar RVM23U32Features = [Feature32Bit,
FeatureStdExtI,
FeatureStdExtM,
- FeatureStdExtZba,
- FeatureStdExtZbb,
- FeatureStdExtZbs,
+ FeatureStdExtB,
FeatureStdExtZicond,
FeatureStdExtZihintpause,
FeatureStdExtZihintntl,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index a89ae1742bb3af..7624071f4f93ec 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -592,13 +592,13 @@
; RVI20U64: .attribute 5, "rv64i2p1"
; RVA20U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zmmul1p0_za128rs1p0"
; RVA20S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zmmul1p0_za128rs1p0_ssccptr1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0"
-; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
-; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0"
-; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0"
-; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
-; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
-; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
-; RVM23U32: .attribute 5, "rv32i2p1_m2p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zmmul1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0"
+; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
+; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0"
+; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0"
+; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
+; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
+; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
+; RVM23U32: .attribute 5, "rv32i2p1_m2p0_b1p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zmmul1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0"
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
>From 59770a43826f19ed2a735b1e461a43c63bd456bf Mon Sep 17 00:00:00 2001
From: c8ef <c8ef at outlook.com>
Date: Sun, 10 Nov 2024 15:23:58 +0800
Subject: [PATCH 02/31] [NFC] Correct imprecise file location in the comment.
(#115630)
---
compiler-rt/lib/ctx_profile/CtxInstrContextNode.h | 6 +++---
llvm/include/llvm/ProfileData/CtxInstrContextNode.h | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/compiler-rt/lib/ctx_profile/CtxInstrContextNode.h b/compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
index 3b0cbcdd49c254..36a996632b71e3 100644
--- a/compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
+++ b/compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
@@ -8,9 +8,9 @@
//==============================================================================
//
// NOTE!
-// llvm/lib/ProfileData/CtxInstrContextNode.h and
+// llvm/include/llvm/ProfileData/CtxInstrContextNode.h and
// compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
-// must be exact copies of each other
+// must be exact copies of each other.
//
// compiler-rt creates these objects as part of the instrumentation runtime for
// contextual profiling. LLVM only consumes them to convert a contextual tree
@@ -114,4 +114,4 @@ class ContextNode final {
};
} // namespace ctx_profile
} // namespace llvm
-#endif
\ No newline at end of file
+#endif
diff --git a/llvm/include/llvm/ProfileData/CtxInstrContextNode.h b/llvm/include/llvm/ProfileData/CtxInstrContextNode.h
index 3b0cbcdd49c254..36a996632b71e3 100644
--- a/llvm/include/llvm/ProfileData/CtxInstrContextNode.h
+++ b/llvm/include/llvm/ProfileData/CtxInstrContextNode.h
@@ -8,9 +8,9 @@
//==============================================================================
//
// NOTE!
-// llvm/lib/ProfileData/CtxInstrContextNode.h and
+// llvm/include/llvm/ProfileData/CtxInstrContextNode.h and
// compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
-// must be exact copies of each other
+// must be exact copies of each other.
//
// compiler-rt creates these objects as part of the instrumentation runtime for
// contextual profiling. LLVM only consumes them to convert a contextual tree
@@ -114,4 +114,4 @@ class ContextNode final {
};
} // namespace ctx_profile
} // namespace llvm
-#endif
\ No newline at end of file
+#endif
>From 4edd711b4d7ec60117bf77ab79491dba8cf3bb76 Mon Sep 17 00:00:00 2001
From: Durgadoss R <durgadossr at nvidia.com>
Date: Sun, 10 Nov 2024 13:44:42 +0530
Subject: [PATCH 03/31] [NVPTX] Add TMA bulk tensor prefetch intrinsics
(#115527)
This patch adds NVVM intrinsics and NVPTX codegen for:
* cp.async.bulk.tensor.prefetch.1D -> 5D variants, supporting both Tile
and Im2Col modes. These intrinsics optionally support cache_hints as
indicated by the boolean flag argument.
* Lit tests are added for all combinations of these intrinsics in cp-async-bulk-tensor-prefetch.ll.
* The generated PTX is verified with a 12.3 ptxas executable.
* Added docs for these intrinsics in NVPTXUsage.rst file.
* PTX Spec reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-bulk-prefetch-tensor
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
---
llvm/docs/NVPTXUsage.rst | 64 ++++++++
llvm/include/llvm/IR/IntrinsicsNVVM.td | 24 +++
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 104 +++++++++++--
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 1 +
llvm/lib/Target/NVPTX/NVPTXIntrinsics.td | 46 ++++++
.../NVPTX/cp-async-bulk-tensor-prefetch.ll | 144 ++++++++++++++++++
6 files changed, 369 insertions(+), 14 deletions(-)
create mode 100644 llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll
diff --git a/llvm/docs/NVPTXUsage.rst b/llvm/docs/NVPTXUsage.rst
index dca8fd9a0bca0b..2152de9709dc6e 100644
--- a/llvm/docs/NVPTXUsage.rst
+++ b/llvm/docs/NVPTXUsage.rst
@@ -599,6 +599,70 @@ described in the ``s2g.tile`` mode intrinsics above.
For more information, refer PTX ISA
`<https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cp-async-bulk-tensor>`_.
+'``llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.[1-5]d``'
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+
+.. code-block:: llvm
+
+ declare void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.1d(ptr %tensor_map, i32 %d0, i64 %ch, i1 %flag_ch)
+ declare void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.2d(..., i32 %d0, i32 %d1, ...)
+ declare void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.3d(..., i32 %d0, i32 %d1, i32 %d2, ...)
+ declare void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.4d(..., i32 %d0, i32 %d1, i32 %d2, i32 %d3, ...)
+ declare void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.5d(..., i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, ...)
+
+Overview:
+"""""""""
+
+The '``@llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.[1-5]d``' intrinsics
+correspond to the ``cp.async.bulk.prefetch.tensor.[1-5]d.L2.global*`` set
+of PTX instructions. These instructions initiate an asynchronous prefetch
+of tensor data from global memory to the L2 cache. In tile mode, the
+multi-dimensional layout of the source tensor is preserved at the destination.
+The dimension of the tensor data ranges from 1d to 5d with the coordinates
+specified by the ``i32 %d0 ... i32 %d4`` arguments.
+
+* The last argument to these intrinsics is a boolean flag
+ indicating support for cache_hint. This flag argument must
+ be a compile-time constant. When set, it indicates a valid
+ cache_hint (``i64 %ch``) and generates the ``.L2::cache_hint``
+ variant of the PTX instruction.
+
+For more information, refer PTX ISA
+`<https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-bulk-prefetch-tensor>`_.
+
+'``llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.[1-5]d``'
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+
+.. code-block:: llvm
+
+ declare void @llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.3d(ptr %tensor_map, i32 %d0, i32 %d1, i32 %d2, i16 %im2col0, i64 %ch, i1 %flag_ch)
+ declare void @llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.4d(..., i32 %d0, i32 %d1, i32 %d2, i32 %d3, i16 %im2col0, i16 %im2col1, ...)
+ declare void @llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.5d(..., i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %im2col0, i16 %im2col1, i16 %im2col2, ...)
+
+Overview:
+"""""""""
+
+The '``@llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.[1-5]d``' intrinsics
+correspond to the ``cp.async.bulk.prefetch.tensor.[1-5]d.L2.global*`` set
+of PTX instructions. These instructions initiate an asynchronous prefetch
+of tensor data from global memory to the L2 cache. In im2col mode, some
+dimensions of the source tensor are unrolled into a single dimensional
+column at the destination. In this mode, the tensor has to be at least
+three-dimensional. Along with the tensor coordinates, im2col offsets are
+also specified (denoted by ``i16 im2col0...i16 %im2col2``). The number
+of im2col offsets is two less than the number of dimensions of the tensor
+operation. The last argument to these intrinsics is a boolean flag, with
+the same functionality as described in the ``tile`` mode intrinsics above.
+
+For more information, refer PTX ISA
+`<https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cp-async-bulk-prefetch-tensor>`_.
+
Other Intrinsics
----------------
diff --git a/llvm/include/llvm/IR/IntrinsicsNVVM.td b/llvm/include/llvm/IR/IntrinsicsNVVM.td
index 049d843015d5ae..115fcee0b04f22 100644
--- a/llvm/include/llvm/IR/IntrinsicsNVVM.td
+++ b/llvm/include/llvm/IR/IntrinsicsNVVM.td
@@ -613,6 +613,28 @@ class CP_ASYNC_BULK_TENSOR_S2G_INTR<int dim, string mode> {
ImmArg<ArgIndex<FlagsStartIdx>>];
}
+class CP_ASYNC_BULK_TENSOR_PREFETCH_INTR<int dim, string mode> {
+ string Name = "int_nvvm_cp_async_bulk_tensor_prefetch_" # mode # "_" # dim # "d";
+
+ bit IsIm2Col = !if(!eq(mode, "im2col"), 1, 0);
+ int NumIm2ColOffsets = !if(IsIm2Col, !add(dim, -2), 0);
+ list<LLVMType> Im2ColOffsetsTy = !listsplat(llvm_i16_ty, NumIm2ColOffsets);
+ list<LLVMType> TensorDimsTy = !listsplat(llvm_i32_ty, dim);
+ list<LLVMType> ArgsTy = !listconcat(
+ [llvm_ptr_ty], // tensormap_ptr
+ TensorDimsTy, // actual tensor dims
+ Im2ColOffsetsTy, // im2col offsets
+ [llvm_i64_ty, // cache_hint
+ llvm_i1_ty] // Flag for cache_hint
+ );
+
+ int TempFlagsStartIdx = !add(dim, 2);
+ int FlagsStartIdx = !add(TempFlagsStartIdx, NumIm2ColOffsets);
+ list<IntrinsicProperty> IntrProp = [IntrConvergent,
+ ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>,
+ ImmArg<ArgIndex<FlagsStartIdx>>];
+}
+
let TargetPrefix = "nvvm" in {
def int_nvvm_prmt : ClangBuiltin<"__nvvm_prmt">,
DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
@@ -4902,6 +4924,8 @@ foreach dim = [1, 2, 3, 4, 5] in {
def g2s.Name : DefaultAttrsIntrinsic<[], g2s.ArgsTy, g2s.IntrProp>;
foreach s2g = [CP_ASYNC_BULK_TENSOR_S2G_INTR<dim, mode>] in
def s2g.Name : DefaultAttrsIntrinsic<[], s2g.ArgsTy, s2g.IntrProp>;
+ foreach prefetch = [CP_ASYNC_BULK_TENSOR_PREFETCH_INTR<dim, mode>] in
+ def prefetch.Name : DefaultAttrsIntrinsic<[], prefetch.ArgsTy, prefetch.IntrProp>;
}
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index 0c472c456bd5dd..2e7cf10d48cb62 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -4175,6 +4175,10 @@ bool NVPTXScopes::empty() const { return Scopes.size() == 0; }
return CP_ASYNC_BULK_TENSOR_OPCODE(G2S, dim, mode, ); \
}()
+#define GET_CP_ASYNC_BULK_TENSOR_OPCODE_PREFETCH(dim, mode) \
+ (IsCacheHint ? NVPTX::CP_ASYNC_BULK_TENSOR_PREFETCH_##dim##_##mode##_CH \
+ : NVPTX::CP_ASYNC_BULK_TENSOR_PREFETCH_##dim##_##mode)
+
static unsigned GetCpAsyncBulkTensorS2GOpcode(size_t Dim, bool IsShared32,
bool IsCacheHint, bool IsIm2Col) {
if (IsIm2Col) {
@@ -4242,6 +4246,55 @@ static unsigned GetCpAsyncBulkTensorG2SOpcode(size_t Dim, bool IsShared32,
}
}
+static unsigned GetCpAsyncBulkTensorPrefetchOpcode(size_t Dim, bool IsCacheHint,
+ bool IsIm2Col) {
+ if (IsIm2Col) {
+ switch (Dim) {
+ case 3:
+ return GET_CP_ASYNC_BULK_TENSOR_OPCODE_PREFETCH(3D, IM2COL);
+ case 4:
+ return GET_CP_ASYNC_BULK_TENSOR_OPCODE_PREFETCH(4D, IM2COL);
+ case 5:
+ return GET_CP_ASYNC_BULK_TENSOR_OPCODE_PREFETCH(5D, IM2COL);
+ default:
+ llvm_unreachable("Invalid Dimension in im2col mode for "
+ "GetCpAsyncBulkTensorPrefetchOpcode.");
+ }
+ } else {
+ switch (Dim) {
+ case 1:
+ return GET_CP_ASYNC_BULK_TENSOR_OPCODE_PREFETCH(1D, TILE);
+ case 2:
+ return GET_CP_ASYNC_BULK_TENSOR_OPCODE_PREFETCH(2D, TILE);
+ case 3:
+ return GET_CP_ASYNC_BULK_TENSOR_OPCODE_PREFETCH(3D, TILE);
+ case 4:
+ return GET_CP_ASYNC_BULK_TENSOR_OPCODE_PREFETCH(4D, TILE);
+ case 5:
+ return GET_CP_ASYNC_BULK_TENSOR_OPCODE_PREFETCH(5D, TILE);
+ default:
+ llvm_unreachable("Invalid Dimension in tile mode for "
+ "GetCpAsyncBulkTensorPrefetchOpcode.");
+ }
+ }
+}
+
+static size_t GetDimsFromIntrinsic(unsigned IID) {
+ switch (IID) {
+ case Intrinsic::nvvm_cp_async_bulk_tensor_g2s_im2col_3d:
+ case Intrinsic::nvvm_cp_async_bulk_tensor_prefetch_im2col_3d:
+ return 3;
+ case Intrinsic::nvvm_cp_async_bulk_tensor_g2s_im2col_4d:
+ case Intrinsic::nvvm_cp_async_bulk_tensor_prefetch_im2col_4d:
+ return 4;
+ case Intrinsic::nvvm_cp_async_bulk_tensor_g2s_im2col_5d:
+ case Intrinsic::nvvm_cp_async_bulk_tensor_prefetch_im2col_5d:
+ return 5;
+ default:
+ llvm_unreachable("Invalid im2col intrinsic in GetDimsFromIntrinsic.");
+ }
+}
+
void NVPTXDAGToDAGISel::SelectCpAsyncBulkTensorG2SCommon(SDNode *N,
bool IsIm2Col) {
// We have {Chain, Intrinsic-ID} followed by the actual intrisic args:
@@ -4250,21 +4303,8 @@ void NVPTXDAGToDAGISel::SelectCpAsyncBulkTensorG2SCommon(SDNode *N,
// multicast_flag, cache_hint_flag}
// NumOperands = {Chain, IID} + {Actual intrinsic args}
// = {2} + {7 + dims + im2col_offsets}
- auto getDimsFromIntrinsic = [](unsigned IID) {
- switch (IID) {
- case Intrinsic::nvvm_cp_async_bulk_tensor_g2s_im2col_3d:
- return 3;
- case Intrinsic::nvvm_cp_async_bulk_tensor_g2s_im2col_4d:
- return 4;
- case Intrinsic::nvvm_cp_async_bulk_tensor_g2s_im2col_5d:
- return 5;
- default:
- llvm_unreachable(
- "Invalid im2col intrinsic in SelectCpAsyncBulkTensorG2SCommon.");
- }
- };
size_t NumOps = N->getNumOperands();
- size_t NumDims = IsIm2Col ? getDimsFromIntrinsic(N->getConstantOperandVal(1))
+ size_t NumDims = IsIm2Col ? GetDimsFromIntrinsic(N->getConstantOperandVal(1))
: (NumOps - 9);
// Offsets is always 'NumDims - 2' and only for im2col mode
size_t NumOffsets = IsIm2Col ? (NumDims - 2) : 0;
@@ -4316,6 +4356,30 @@ void NVPTXDAGToDAGISel::SelectCpAsyncBulkTensorS2GCommon(SDNode *N,
ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops));
}
+void NVPTXDAGToDAGISel::SelectCpAsyncBulkTensorPrefetchCommon(SDNode *N,
+ bool IsIm2Col) {
+ // We have {Chain, Intrinsic-ID} followed by the actual intrisic args:
+ // {src, dims{d0...dN}, im2col_offsets{dims-2}
+ // cache_hint, cache_hint_flag}
+ // NumOperands = {Chain, IID} + {Actual intrinsic args}
+ // = {2} + {3 + dims + im2col_offsets}
+ size_t NumOps = N->getNumOperands();
+ size_t NumDims = IsIm2Col ? GetDimsFromIntrinsic(N->getConstantOperandVal(1))
+ : (NumOps - 5);
+ // Offsets is always 'NumDims - 2' and only for im2col mode
+ size_t NumOffsets = IsIm2Col ? (NumDims - 2) : 0;
+ bool IsCacheHint = N->getConstantOperandVal(NumOps - 1) == 1;
+ size_t NumArgs = NumDims + NumOffsets + (IsCacheHint ? 2 : 1);
+
+ SDLoc DL(N);
+ SmallVector<SDValue, 12> Ops(N->ops().slice(2, NumArgs));
+ Ops.push_back(N->getOperand(0)); // Chain operand
+
+ unsigned Opcode =
+ GetCpAsyncBulkTensorPrefetchOpcode(NumDims, IsCacheHint, IsIm2Col);
+ ReplaceNode(N, CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops));
+}
+
bool NVPTXDAGToDAGISel::tryIntrinsicVoid(SDNode *N) {
unsigned IID = N->getConstantOperandVal(1);
switch (IID) {
@@ -4345,5 +4409,17 @@ bool NVPTXDAGToDAGISel::tryIntrinsicVoid(SDNode *N) {
case Intrinsic::nvvm_cp_async_bulk_tensor_g2s_im2col_5d:
SelectCpAsyncBulkTensorG2SCommon(N, /*IsIm2Col=*/true);
return true;
+ case Intrinsic::nvvm_cp_async_bulk_tensor_prefetch_tile_1d:
+ case Intrinsic::nvvm_cp_async_bulk_tensor_prefetch_tile_2d:
+ case Intrinsic::nvvm_cp_async_bulk_tensor_prefetch_tile_3d:
+ case Intrinsic::nvvm_cp_async_bulk_tensor_prefetch_tile_4d:
+ case Intrinsic::nvvm_cp_async_bulk_tensor_prefetch_tile_5d:
+ SelectCpAsyncBulkTensorPrefetchCommon(N);
+ return true;
+ case Intrinsic::nvvm_cp_async_bulk_tensor_prefetch_im2col_3d:
+ case Intrinsic::nvvm_cp_async_bulk_tensor_prefetch_im2col_4d:
+ case Intrinsic::nvvm_cp_async_bulk_tensor_prefetch_im2col_5d:
+ SelectCpAsyncBulkTensorPrefetchCommon(N, /*IsIm2Col=*/true);
+ return true;
}
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
index 6aa4e9f615a481..d6c80a31b7463d 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
@@ -94,6 +94,7 @@ class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
void SelectI128toV2I64(SDNode *N);
void SelectCpAsyncBulkTensorG2SCommon(SDNode *N, bool IsIm2Col = false);
void SelectCpAsyncBulkTensorS2GCommon(SDNode *N, bool IsIm2Col = false);
+ void SelectCpAsyncBulkTensorPrefetchCommon(SDNode *N, bool IsIm2Col = false);
inline SDValue getI32Imm(unsigned Imm, const SDLoc &DL) {
return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
index 536be22510703d..5878940812f62b 100644
--- a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+++ b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
@@ -605,6 +605,52 @@ foreach dim = [1, 2, 3, 4, 5] in {
}
}
+// TMA Prefetch from Global memory to L2 cache
+class PREFETCH_STRINGS<int dim, string mode, bit ch> {
+ string prefix = "cp.async.bulk.prefetch.tensor";
+ string dir = "L2.global";
+ string inst_name = prefix
+ # "." # dim # "d"
+ # "." # dir
+ # "." # mode
+ # !if(ch, ".L2::cache_hint", "");
+ string intr_name = "CP_ASYNC_BULK_TENSOR_PREFETCH_"
+ # dim # "D"
+ # !if(!eq(mode, "tile"), "_TILE", "_IM2COL");
+}
+
+multiclass CP_ASYNC_BULK_TENSOR_PREFETCH_INTR<int dim, string mode> {
+ defvar dims_dag = !dag(ins, !listsplat(Int32Regs, dim), !foreach(i, !range(dim), "d" # i));
+ defvar dims_str = !interleave(!foreach(i, !range(dim), "$d" # i), ", ");
+ defvar asm_str_default = " [$tmap, {{" # dims_str # "}}]";
+
+ defvar num_im2col = !if(!ge(dim, 3), !add(dim, -2), 0);
+ defvar im2col_dag = !if(!eq(mode, "im2col"),
+ !dag(ins, !listsplat(Int16Regs, num_im2col), !foreach(i, !range(num_im2col), "im2col" # i)),
+ (ins));
+ defvar im2col_str = !interleave(!foreach(i, !range(num_im2col), "$im2col" # i), ", ");
+ defvar im2col_asm_str = ", {{" # im2col_str # "}}";
+
+ defvar asm_str = !if(!eq(mode, "im2col"),
+ !strconcat(asm_str_default, im2col_asm_str), asm_str_default);
+
+ def "": NVPTXInst<(outs),
+ !con((ins Int64Regs:$tmap), dims_dag, im2col_dag),
+ !strconcat(PREFETCH_STRINGS<dim, mode, 0>.inst_name, asm_str, ";"), []>,
+ Requires<[hasPTX<80>, hasSM<90>]>;
+ def _CH: NVPTXInst<(outs),
+ !con((ins Int64Regs:$tmap), dims_dag, im2col_dag, (ins Int64Regs:$ch)),
+ !strconcat(PREFETCH_STRINGS<dim, mode, 1>.inst_name, asm_str, ", $ch;"), []>,
+ Requires<[hasPTX<80>, hasSM<90>]>;
+}
+
+foreach dim = [1, 2, 3, 4, 5] in {
+ foreach mode = !if(!ge(dim, 3), ["tile", "im2col"], ["tile"]) in {
+ defm PREFETCH_STRINGS<dim, mode, 0>.intr_name :
+ CP_ASYNC_BULK_TENSOR_PREFETCH_INTR<dim, mode>;
+ }
+}
+
//-----------------------------------
// MBarrier Functions
//-----------------------------------
diff --git a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll
new file mode 100644
index 00000000000000..cb3b0c03f75d09
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll
@@ -0,0 +1,144 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_90 -mattr=+ptx80| FileCheck --check-prefixes=CHECK-PTX %s
+; RUN: %if ptxas-12.3 %{ llc < %s -march=nvptx64 -mcpu=sm_90 -mattr=+ptx80| %ptxas-verify -arch=sm_90 %}
+
+target triple = "nvptx64-nvidia-cuda"
+
+declare void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.1d(ptr %tm, i32 %d0, i64 %ch, i1 %flag);
+declare void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.2d(ptr %tm, i32 %d0, i32 %d1, i64 %ch, i1 %flag);
+declare void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.3d(ptr %tm, i32 %d0, i32 %d1, i32 %d2, i64 %ch, i1 %flag);
+declare void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.4d(ptr %tm, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i64 %ch, i1 %flag);
+declare void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.5d(ptr %tm, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i64 %ch, i1 %flag);
+
+declare void @llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.3d(ptr %tm, i32 %d0, i32 %d1, i32 %d2, i16 %im2col0, i64 %ch, i1 %f1);
+declare void @llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.4d(ptr %tm, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i16 %im2col0, i16 %im2col1, i64 %ch, i1 %f1);
+declare void @llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.5d(ptr %tm, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %im2col0, i16 %im2col1, i16 %im2col2, i64 %ch, i1 %f1);
+
+; CHECK-LABEL: cp_async_bulk_tensor_prefetch_tile_1d
+define void @cp_async_bulk_tensor_prefetch_tile_1d(ptr %tmap, i32 %d0, i64 %ch) {
+; CHECK-PTX-LABEL: cp_async_bulk_tensor_prefetch_tile_1d(
+; CHECK-PTX: {
+; CHECK-PTX-NEXT: .reg .b32 %r<2>;
+; CHECK-PTX-NEXT: .reg .b64 %rd<3>;
+; CHECK-PTX-EMPTY:
+; CHECK-PTX-NEXT: // %bb.0:
+; CHECK-PTX-NEXT: ld.param.u64 %rd1, [cp_async_bulk_tensor_prefetch_tile_1d_param_0];
+; CHECK-PTX-NEXT: ld.param.u32 %r1, [cp_async_bulk_tensor_prefetch_tile_1d_param_1];
+; CHECK-PTX-NEXT: cp.async.bulk.prefetch.tensor.1d.L2.global.tile [%rd1, {%r1}];
+; CHECK-PTX-NEXT: ld.param.u64 %rd2, [cp_async_bulk_tensor_prefetch_tile_1d_param_2];
+; CHECK-PTX-NEXT: cp.async.bulk.prefetch.tensor.1d.L2.global.tile.L2::cache_hint [%rd1, {%r1}], %rd2;
+; CHECK-PTX-NEXT: ret;
+ tail call void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.1d(ptr %tmap, i32 %d0, i64 undef, i1 0)
+ tail call void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.1d(ptr %tmap, i32 %d0, i64 %ch, i1 1)
+ ret void
+}
+
+; CHECK-LABEL: cp_async_bulk_tensor_prefetch_tile_2d
+define void @cp_async_bulk_tensor_prefetch_tile_2d(i32 %flag, ptr %tmap, i32 %d0, i32 %d1, i64 %ch) {
+; CHECK-PTX-LABEL: cp_async_bulk_tensor_prefetch_tile_2d(
+; CHECK-PTX: {
+; CHECK-PTX-NEXT: .reg .b32 %r<3>;
+; CHECK-PTX-NEXT: .reg .b64 %rd<3>;
+; CHECK-PTX-EMPTY:
+; CHECK-PTX-NEXT: // %bb.0:
+; CHECK-PTX-NEXT: ld.param.u64 %rd1, [cp_async_bulk_tensor_prefetch_tile_2d_param_1];
+; CHECK-PTX-NEXT: ld.param.u32 %r1, [cp_async_bulk_tensor_prefetch_tile_2d_param_2];
+; CHECK-PTX-NEXT: ld.param.u32 %r2, [cp_async_bulk_tensor_prefetch_tile_2d_param_3];
+; CHECK-PTX-NEXT: cp.async.bulk.prefetch.tensor.2d.L2.global.tile [%rd1, {%r1, %r2}];
+; CHECK-PTX-NEXT: ld.param.u64 %rd2, [cp_async_bulk_tensor_prefetch_tile_2d_param_4];
+; CHECK-PTX-NEXT: cp.async.bulk.prefetch.tensor.2d.L2.global.tile.L2::cache_hint [%rd1, {%r1, %r2}], %rd2;
+; CHECK-PTX-NEXT: ret;
+ tail call void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.2d(ptr %tmap, i32 %d0, i32 %d1, i64 undef, i1 0)
+ tail call void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.2d(ptr %tmap, i32 %d0, i32 %d1, i64 %ch, i1 1)
+ ret void
+}
+
+; CHECK-LABEL: cp_async_bulk_tensor_prefetch_3d
+define void @cp_async_bulk_tensor_prefetch_3d(i32 %flag, ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i16 %im2col0, i64 %ch) {
+; CHECK-PTX-LABEL: cp_async_bulk_tensor_prefetch_3d(
+; CHECK-PTX: {
+; CHECK-PTX-NEXT: .reg .b16 %rs<2>;
+; CHECK-PTX-NEXT: .reg .b32 %r<4>;
+; CHECK-PTX-NEXT: .reg .b64 %rd<3>;
+; CHECK-PTX-EMPTY:
+; CHECK-PTX-NEXT: // %bb.0:
+; CHECK-PTX-NEXT: ld.param.u64 %rd1, [cp_async_bulk_tensor_prefetch_3d_param_1];
+; CHECK-PTX-NEXT: ld.param.u32 %r1, [cp_async_bulk_tensor_prefetch_3d_param_2];
+; CHECK-PTX-NEXT: ld.param.u32 %r2, [cp_async_bulk_tensor_prefetch_3d_param_3];
+; CHECK-PTX-NEXT: ld.param.u32 %r3, [cp_async_bulk_tensor_prefetch_3d_param_4];
+; CHECK-PTX-NEXT: cp.async.bulk.prefetch.tensor.3d.L2.global.tile [%rd1, {%r1, %r2, %r3}];
+; CHECK-PTX-NEXT: ld.param.u64 %rd2, [cp_async_bulk_tensor_prefetch_3d_param_6];
+; CHECK-PTX-NEXT: cp.async.bulk.prefetch.tensor.3d.L2.global.tile.L2::cache_hint [%rd1, {%r1, %r2, %r3}], %rd2;
+; CHECK-PTX-NEXT: ld.param.u16 %rs1, [cp_async_bulk_tensor_prefetch_3d_param_5];
+; CHECK-PTX-NEXT: cp.async.bulk.prefetch.tensor.3d.L2.global.im2col [%rd1, {%r1, %r2, %r3}], {%rs1};
+; CHECK-PTX-NEXT: cp.async.bulk.prefetch.tensor.3d.L2.global.im2col.L2::cache_hint [%rd1, {%r1, %r2, %r3}], {%rs1}, %rd2;
+; CHECK-PTX-NEXT: ret;
+ tail call void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.3d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i64 undef, i1 0)
+ tail call void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.3d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i64 %ch, i1 1)
+
+ tail call void @llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.3d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i16 %im2col0, i64 undef, i1 0)
+ tail call void @llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.3d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i16 %im2col0, i64 %ch, i1 1)
+ ret void
+}
+
+; CHECK-LABEL: cp_async_bulk_tensor_prefetch_4d
+define void @cp_async_bulk_tensor_prefetch_4d(i32 %flag, ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i16 %im2col0, i16 %im2col1, i64 %ch) {
+; CHECK-PTX-LABEL: cp_async_bulk_tensor_prefetch_4d(
+; CHECK-PTX: {
+; CHECK-PTX-NEXT: .reg .b16 %rs<3>;
+; CHECK-PTX-NEXT: .reg .b32 %r<5>;
+; CHECK-PTX-NEXT: .reg .b64 %rd<3>;
+; CHECK-PTX-EMPTY:
+; CHECK-PTX-NEXT: // %bb.0:
+; CHECK-PTX-NEXT: ld.param.u64 %rd1, [cp_async_bulk_tensor_prefetch_4d_param_1];
+; CHECK-PTX-NEXT: ld.param.u32 %r1, [cp_async_bulk_tensor_prefetch_4d_param_2];
+; CHECK-PTX-NEXT: ld.param.u32 %r2, [cp_async_bulk_tensor_prefetch_4d_param_3];
+; CHECK-PTX-NEXT: ld.param.u32 %r3, [cp_async_bulk_tensor_prefetch_4d_param_4];
+; CHECK-PTX-NEXT: ld.param.u32 %r4, [cp_async_bulk_tensor_prefetch_4d_param_5];
+; CHECK-PTX-NEXT: cp.async.bulk.prefetch.tensor.4d.L2.global.tile [%rd1, {%r1, %r2, %r3, %r4}];
+; CHECK-PTX-NEXT: ld.param.u64 %rd2, [cp_async_bulk_tensor_prefetch_4d_param_8];
+; CHECK-PTX-NEXT: cp.async.bulk.prefetch.tensor.4d.L2.global.tile.L2::cache_hint [%rd1, {%r1, %r2, %r3, %r4}], %rd2;
+; CHECK-PTX-NEXT: ld.param.u16 %rs1, [cp_async_bulk_tensor_prefetch_4d_param_6];
+; CHECK-PTX-NEXT: ld.param.u16 %rs2, [cp_async_bulk_tensor_prefetch_4d_param_7];
+; CHECK-PTX-NEXT: cp.async.bulk.prefetch.tensor.4d.L2.global.im2col [%rd1, {%r1, %r2, %r3, %r4}], {%rs1, %rs2};
+; CHECK-PTX-NEXT: cp.async.bulk.prefetch.tensor.4d.L2.global.im2col.L2::cache_hint [%rd1, {%r1, %r2, %r3, %r4}], {%rs1, %rs2}, %rd2;
+; CHECK-PTX-NEXT: ret;
+ tail call void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.4d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i64 undef, i1 0)
+ tail call void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.4d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i64 %ch, i1 1)
+
+ tail call void @llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.4d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i16 %im2col0, i16 %im2col1, i64 undef, i1 0)
+ tail call void @llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.4d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i16 %im2col0, i16 %im2col1, i64 %ch, i1 1)
+ ret void
+}
+
+; CHECK-LABEL: cp_async_bulk_tensor_prefetch_5d
+define void @cp_async_bulk_tensor_prefetch_5d(i32 %flag, ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %im2col0, i16 %im2col1, i16 %im2col2, i64 %ch) {
+; CHECK-PTX-LABEL: cp_async_bulk_tensor_prefetch_5d(
+; CHECK-PTX: {
+; CHECK-PTX-NEXT: .reg .b16 %rs<4>;
+; CHECK-PTX-NEXT: .reg .b32 %r<6>;
+; CHECK-PTX-NEXT: .reg .b64 %rd<3>;
+; CHECK-PTX-EMPTY:
+; CHECK-PTX-NEXT: // %bb.0:
+; CHECK-PTX-NEXT: ld.param.u64 %rd1, [cp_async_bulk_tensor_prefetch_5d_param_1];
+; CHECK-PTX-NEXT: ld.param.u32 %r1, [cp_async_bulk_tensor_prefetch_5d_param_2];
+; CHECK-PTX-NEXT: ld.param.u32 %r2, [cp_async_bulk_tensor_prefetch_5d_param_3];
+; CHECK-PTX-NEXT: ld.param.u32 %r3, [cp_async_bulk_tensor_prefetch_5d_param_4];
+; CHECK-PTX-NEXT: ld.param.u32 %r4, [cp_async_bulk_tensor_prefetch_5d_param_5];
+; CHECK-PTX-NEXT: ld.param.u32 %r5, [cp_async_bulk_tensor_prefetch_5d_param_6];
+; CHECK-PTX-NEXT: cp.async.bulk.prefetch.tensor.5d.L2.global.tile [%rd1, {%r1, %r2, %r3, %r4, %r5}];
+; CHECK-PTX-NEXT: ld.param.u64 %rd2, [cp_async_bulk_tensor_prefetch_5d_param_10];
+; CHECK-PTX-NEXT: cp.async.bulk.prefetch.tensor.5d.L2.global.tile.L2::cache_hint [%rd1, {%r1, %r2, %r3, %r4, %r5}], %rd2;
+; CHECK-PTX-NEXT: ld.param.u16 %rs1, [cp_async_bulk_tensor_prefetch_5d_param_7];
+; CHECK-PTX-NEXT: ld.param.u16 %rs2, [cp_async_bulk_tensor_prefetch_5d_param_8];
+; CHECK-PTX-NEXT: ld.param.u16 %rs3, [cp_async_bulk_tensor_prefetch_5d_param_9];
+; CHECK-PTX-NEXT: cp.async.bulk.prefetch.tensor.5d.L2.global.im2col [%rd1, {%r1, %r2, %r3, %r4, %r5}], {%rs1, %rs2, %rs3};
+; CHECK-PTX-NEXT: cp.async.bulk.prefetch.tensor.5d.L2.global.im2col.L2::cache_hint [%rd1, {%r1, %r2, %r3, %r4, %r5}], {%rs1, %rs2, %rs3}, %rd2;
+; CHECK-PTX-NEXT: ret;
+ tail call void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.5d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i64 undef, i1 0)
+ tail call void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.5d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i64 %ch, i1 1)
+
+ tail call void @llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.5d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %im2col0, i16 %im2col1, i16 %im2col2, i64 undef, i1 0)
+ tail call void @llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.5d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %im2col0, i16 %im2col1, i16 %im2col2, i64 %ch, i1 1)
+ ret void
+}
>From d822c099eeacc69f6bf834a6373a41d0c9f84a3e Mon Sep 17 00:00:00 2001
From: Douglas <8796590+dgg5503 at users.noreply.github.com>
Date: Sun, 10 Nov 2024 00:19:02 -0800
Subject: [PATCH 04/31] [JITLink] Use `rsplit` on `-sectcreate` argument in
llvm-jitlink (#115511)
This accounts for cases where the file path may contain an `@` symbol.
In such cases, the split occurs too early causing argument parsing to
fail.
---
.../Generic/Inputs/{ => sect at create}/sectcreate-data.txt | 0
llvm/test/ExecutionEngine/JITLink/Generic/sectcreate.test | 2 +-
llvm/tools/llvm-jitlink/llvm-jitlink.cpp | 2 +-
3 files changed, 2 insertions(+), 2 deletions(-)
rename llvm/test/ExecutionEngine/JITLink/Generic/Inputs/{ => sect at create}/sectcreate-data.txt (100%)
diff --git a/llvm/test/ExecutionEngine/JITLink/Generic/Inputs/sectcreate-data.txt b/llvm/test/ExecutionEngine/JITLink/Generic/Inputs/sect at create/sectcreate-data.txt
similarity index 100%
rename from llvm/test/ExecutionEngine/JITLink/Generic/Inputs/sectcreate-data.txt
rename to llvm/test/ExecutionEngine/JITLink/Generic/Inputs/sect at create/sectcreate-data.txt
diff --git a/llvm/test/ExecutionEngine/JITLink/Generic/sectcreate.test b/llvm/test/ExecutionEngine/JITLink/Generic/sectcreate.test
index c09513a7d3707c..08b6372dcf2c73 100644
--- a/llvm/test/ExecutionEngine/JITLink/Generic/sectcreate.test
+++ b/llvm/test/ExecutionEngine/JITLink/Generic/sectcreate.test
@@ -1,6 +1,6 @@
# RUN: llc -filetype=obj -o %t.o %S/Inputs/main-ret-0.ll
# RUN: llvm-jitlink -noexec \
-# RUN: -sectcreate __data,%S/Inputs/sectcreate-data.txt at foo=0 \
+# RUN: -sectcreate __data,%S/Inputs/sect at create/sectcreate-data.txt at foo=0 \
# RUN: %t.o
#
# Use -sectcreate to create a section from a data file.
diff --git a/llvm/tools/llvm-jitlink/llvm-jitlink.cpp b/llvm/tools/llvm-jitlink/llvm-jitlink.cpp
index cc144cda18e1a3..261daae5e67f94 100644
--- a/llvm/tools/llvm-jitlink/llvm-jitlink.cpp
+++ b/llvm/tools/llvm-jitlink/llvm-jitlink.cpp
@@ -1740,7 +1740,7 @@ static Error addSectCreates(Session &S,
StringRef SCArg(*SCItr);
- auto [SectAndFileName, ExtraSymbolsString] = SCArg.split('@');
+ auto [SectAndFileName, ExtraSymbolsString] = SCArg.rsplit('@');
auto [SectName, FileName] = SectAndFileName.rsplit(',');
if (SectName.empty())
return make_error<StringError>("In -sectcreate=" + SCArg +
>From 27bf45aa36386136db179c494358670a994a98a5 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Sun, 10 Nov 2024 17:07:25 +0800
Subject: [PATCH 05/31] [InstCombine] Fix poison safety of folding
shufflevector into select (#115483)
We are allowed to fold shufflevector into select iff the condition is
guaranteed not to be poison or the RHS is a poison.
Alive2: https://alive2.llvm.org/ce/z/28zEWR
Closes https://github.com/llvm/llvm-project/issues/115465.
---
.../Transforms/InstCombine/InstCombineVectorOps.cpp | 4 +++-
llvm/test/Transforms/InstCombine/vec_shuffle.ll | 12 ++++++++++++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
index 454fe5a91d375a..ede89b099e8deb 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
@@ -2904,7 +2904,9 @@ Instruction *InstCombinerImpl::visitShuffleVectorInst(ShuffleVectorInst &SVI) {
if (auto *SI = dyn_cast<SelectInst>(LHS)) {
// We cannot do this fold for elementwise select since ShuffleVector is
// not elementwise.
- if (SI->getCondition()->getType()->isIntegerTy()) {
+ if (SI->getCondition()->getType()->isIntegerTy() &&
+ (isa<PoisonValue>(RHS) ||
+ isGuaranteedNotToBePoison(SI->getCondition()))) {
if (Instruction *I = FoldOpIntoSelect(SVI, SI))
return I;
}
diff --git a/llvm/test/Transforms/InstCombine/vec_shuffle.ll b/llvm/test/Transforms/InstCombine/vec_shuffle.ll
index 163d9c9557b239..9fb68b5399c845 100644
--- a/llvm/test/Transforms/InstCombine/vec_shuffle.ll
+++ b/llvm/test/Transforms/InstCombine/vec_shuffle.ll
@@ -2411,6 +2411,18 @@ define <4 x i32> @shuf_same_length_vec_select(<4 x i1> %cond) {
ret <4 x i32> %shuf
}
+; Make sure we do not fold in this case.
+define <4 x i8> @shuf_cmp_may_be_poison(<4 x i8> %x, <4 x i8> %y, i1 %cmp) {
+; CHECK-LABEL: @shuf_cmp_may_be_poison(
+; CHECK-NEXT: [[Y:%.*]] = select i1 [[CMP:%.*]], <4 x i8> [[Y1:%.*]], <4 x i8> <i8 0, i8 poison, i8 0, i8 poison>
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i8> [[Y]], <4 x i8> <i8 poison, i8 1, i8 poison, i8 3>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; CHECK-NEXT: ret <4 x i8> [[TMP1]]
+;
+ %sel = select i1 %cmp, <4 x i8> %y, <4 x i8> <i8 0, i8 poison, i8 0, i8 poison>
+ %shuf = shufflevector <4 x i8> %sel, <4 x i8> <i8 poison, i8 1, i8 poison, i8 3>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+ ret <4 x i8> %shuf
+}
+
declare i1 @cond()
declare <4 x i32> @value()
>From a5a1612deb7af713835b5c8cf22105c5699bc62d Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Sun, 10 Nov 2024 09:17:02 +0000
Subject: [PATCH 06/31] [VPlan] Consistently use DEBUG_TYPE loop-vectorize.
This ensures debug messages in VPlan.cpp are included in the commonly
used -debug-only=loop-vectorize.
---
llvm/lib/Transforms/Vectorize/VPlan.cpp | 2 +-
.../LoopVectorize/RISCV/riscv-vector-reverse.ll | 14 ++------------
2 files changed, 3 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp b/llvm/lib/Transforms/Vectorize/VPlan.cpp
index 08db0d51ef3abb..8b1a4aeb88f81f 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp
@@ -58,7 +58,7 @@ static cl::opt<bool> PrintVPlansInDotFormat(
"vplan-print-in-dot-format", cl::Hidden,
cl::desc("Use dot format instead of plain text when dumping VPlans"));
-#define DEBUG_TYPE "vplan"
+#define DEBUG_TYPE "loop-vectorize"
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
raw_ostream &llvm::operator<<(raw_ostream &OS, const VPValue &V) {
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll b/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
index a38835f5613fd8..d68556fca4774f 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; This is the loop in c++ being vectorize in this file with
;vector.reverse
; #pragma clang loop vectorize_width(4, scalable)
@@ -195,12 +194,7 @@ define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocaptur
; CHECK: IR %indvars.iv.next = add nsw i64 %indvars.iv, -1
; CHECK-NEXT: No successors
; CHECK-NEXT: }
-; CHECK-NEXT: LV: Loop does not require scalar epilogue
-; CHECK-NEXT: LV: Loop does not require scalar epilogue
-; CHECK-NEXT: LV: Interleaving disabled by the pass manager
-; CHECK-NEXT: LV: Loop does not require scalar epilogue
-; CHECK-NEXT: LV: Vectorizing: innermost loop.
-; CHECK-EMPTY:
+; CHECK: LV: Loop does not require scalar epilogue
;
entry:
%cmp7 = icmp sgt i32 %n, 0
@@ -414,11 +408,7 @@ define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocaptur
; CHECK: IR %indvars.iv.next = add nsw i64 %indvars.iv, -1
; CHECK-NEXT: No successors
; CHECK-NEXT: }
-; CHECK-NEXT: LV: Loop does not require scalar epilogue
-; CHECK-NEXT: LV: Loop does not require scalar epilogue
-; CHECK-NEXT: LV: Interleaving disabled by the pass manager
-; CHECK-NEXT: LV: Loop does not require scalar epilogue
-; CHECK-NEXT: LV: Vectorizing: innermost loop.
+; CHECK: LV: Loop does not require scalar epilogue
;
entry:
%cmp7 = icmp sgt i32 %n, 0
>From 81613ddcd6fe04a029c1a15a3454b5b0cd18a24c Mon Sep 17 00:00:00 2001
From: Lang Hames <lhames at gmail.com>
Date: Sun, 10 Nov 2024 20:43:35 +1100
Subject: [PATCH 07/31] [ORC] Move some typedefs from Core.h to a new header,
CoreContainers.h. NFC.
This is a first step towards breaking up Core.h
---
llvm/include/llvm/ExecutionEngine/Orc/Core.h | 18 +------
.../llvm/ExecutionEngine/Orc/CoreContainers.h | 47 +++++++++++++++++++
2 files changed, 48 insertions(+), 17 deletions(-)
create mode 100644 llvm/include/llvm/ExecutionEngine/Orc/CoreContainers.h
diff --git a/llvm/include/llvm/ExecutionEngine/Orc/Core.h b/llvm/include/llvm/ExecutionEngine/Orc/Core.h
index f578455905f210..c755a18020553a 100644
--- a/llvm/include/llvm/ExecutionEngine/Orc/Core.h
+++ b/llvm/include/llvm/ExecutionEngine/Orc/Core.h
@@ -19,6 +19,7 @@
#include "llvm/ADT/IntrusiveRefCntPtr.h"
#include "llvm/ExecutionEngine/JITLink/JITLinkDylib.h"
#include "llvm/ExecutionEngine/JITSymbol.h"
+#include "llvm/ExecutionEngine/Orc/CoreContainers.h"
#include "llvm/ExecutionEngine/Orc/ExecutorProcessControl.h"
#include "llvm/ExecutionEngine/Orc/Shared/ExecutorAddress.h"
#include "llvm/ExecutionEngine/Orc/Shared/ExecutorSymbolDef.h"
@@ -109,23 +110,6 @@ class ResourceManager {
ResourceKey SrcK) = 0;
};
-/// A set of symbol names (represented by SymbolStringPtrs for
-// efficiency).
-using SymbolNameSet = DenseSet<SymbolStringPtr>;
-
-/// A vector of symbol names.
-using SymbolNameVector = std::vector<SymbolStringPtr>;
-
-/// A map from symbol names (as SymbolStringPtrs) to JITSymbols
-/// (address/flags pairs).
-using SymbolMap = DenseMap<SymbolStringPtr, ExecutorSymbolDef>;
-
-/// A map from symbol names (as SymbolStringPtrs) to JITSymbolFlags.
-using SymbolFlagsMap = DenseMap<SymbolStringPtr, JITSymbolFlags>;
-
-/// A map from JITDylibs to sets of symbols.
-using SymbolDependenceMap = DenseMap<JITDylib *, SymbolNameSet>;
-
/// Lookup flags that apply to each dylib in the search order for a lookup.
///
/// If MatchHiddenSymbolsOnly is used (the default) for a given dylib, then
diff --git a/llvm/include/llvm/ExecutionEngine/Orc/CoreContainers.h b/llvm/include/llvm/ExecutionEngine/Orc/CoreContainers.h
new file mode 100644
index 00000000000000..06d5aef0119f9b
--- /dev/null
+++ b/llvm/include/llvm/ExecutionEngine/Orc/CoreContainers.h
@@ -0,0 +1,47 @@
+//===---- CoreContainers.h - Symbol Containers for Core APIs ----*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Symbol container types for core ORC APIs.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_EXECUTIONENGINE_ORC_CORECONTAINERS_H
+#define LLVM_EXECUTIONENGINE_ORC_CORECONTAINERS_H
+
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/DenseSet.h"
+#include "llvm/ExecutionEngine/JITSymbol.h"
+#include "llvm/ExecutionEngine/Orc/Shared/ExecutorSymbolDef.h"
+#include "llvm/ExecutionEngine/Orc/SymbolStringPool.h"
+
+#include <vector>
+
+namespace llvm::orc {
+
+class JITDylib;
+
+/// A set of symbol names (represented by SymbolStringPtrs for
+// efficiency).
+using SymbolNameSet = DenseSet<SymbolStringPtr>;
+
+/// A vector of symbol names.
+using SymbolNameVector = std::vector<SymbolStringPtr>;
+
+/// A map from symbol names (as SymbolStringPtrs) to JITSymbols
+/// (address/flags pairs).
+using SymbolMap = DenseMap<SymbolStringPtr, ExecutorSymbolDef>;
+
+/// A map from symbol names (as SymbolStringPtrs) to JITSymbolFlags.
+using SymbolFlagsMap = DenseMap<SymbolStringPtr, JITSymbolFlags>;
+
+/// A map from JITDylibs to sets of symbols.
+using SymbolDependenceMap = DenseMap<JITDylib *, SymbolNameSet>;
+
+} // End namespace llvm::orc
+
+#endif // LLVM_EXECUTIONENGINE_ORC_CORECONTAINERS_H
>From 3d2849bd151f415b59044736e069c7605339b8e2 Mon Sep 17 00:00:00 2001
From: Lang Hames <lhames at gmail.com>
Date: Sun, 10 Nov 2024 21:02:26 +1100
Subject: [PATCH 08/31] [ORC] Move MaterializationUnit from Core.h into its own
header. NFC.
Continuing Core.h clean-up.
---
llvm/include/llvm/ExecutionEngine/Orc/Core.h | 79 +------------
.../ExecutionEngine/Orc/MaterializationUnit.h | 105 ++++++++++++++++++
2 files changed, 106 insertions(+), 78 deletions(-)
create mode 100644 llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h
diff --git a/llvm/include/llvm/ExecutionEngine/Orc/Core.h b/llvm/include/llvm/ExecutionEngine/Orc/Core.h
index c755a18020553a..119d3d878206fb 100644
--- a/llvm/include/llvm/ExecutionEngine/Orc/Core.h
+++ b/llvm/include/llvm/ExecutionEngine/Orc/Core.h
@@ -21,6 +21,7 @@
#include "llvm/ExecutionEngine/JITSymbol.h"
#include "llvm/ExecutionEngine/Orc/CoreContainers.h"
#include "llvm/ExecutionEngine/Orc/ExecutorProcessControl.h"
+#include "llvm/ExecutionEngine/Orc/MaterializationUnit.h"
#include "llvm/ExecutionEngine/Orc/Shared/ExecutorAddress.h"
#include "llvm/ExecutionEngine/Orc/Shared/ExecutorSymbolDef.h"
#include "llvm/ExecutionEngine/Orc/Shared/WrapperFunctionUtils.h"
@@ -40,7 +41,6 @@ namespace orc {
// Forward declare some classes.
class AsynchronousSymbolQuery;
class ExecutionSession;
-class MaterializationUnit;
class MaterializationResponsibility;
class JITDylib;
class ResourceTracker;
@@ -666,83 +666,6 @@ class MaterializationResponsibility {
SymbolStringPtr InitSymbol;
};
-/// A MaterializationUnit represents a set of symbol definitions that can
-/// be materialized as a group, or individually discarded (when
-/// overriding definitions are encountered).
-///
-/// MaterializationUnits are used when providing lazy definitions of symbols to
-/// JITDylibs. The JITDylib will call materialize when the address of a symbol
-/// is requested via the lookup method. The JITDylib will call discard if a
-/// stronger definition is added or already present.
-class MaterializationUnit {
- friend class ExecutionSession;
- friend class JITDylib;
-
-public:
- static char ID;
-
- struct Interface {
- Interface() = default;
- Interface(SymbolFlagsMap InitalSymbolFlags, SymbolStringPtr InitSymbol)
- : SymbolFlags(std::move(InitalSymbolFlags)),
- InitSymbol(std::move(InitSymbol)) {
- assert((!this->InitSymbol || this->SymbolFlags.count(this->InitSymbol)) &&
- "If set, InitSymbol should appear in InitialSymbolFlags map");
- }
-
- SymbolFlagsMap SymbolFlags;
- SymbolStringPtr InitSymbol;
- };
-
- MaterializationUnit(Interface I)
- : SymbolFlags(std::move(I.SymbolFlags)),
- InitSymbol(std::move(I.InitSymbol)) {}
- virtual ~MaterializationUnit() = default;
-
- /// Return the name of this materialization unit. Useful for debugging
- /// output.
- virtual StringRef getName() const = 0;
-
- /// Return the set of symbols that this source provides.
- const SymbolFlagsMap &getSymbols() const { return SymbolFlags; }
-
- /// Returns the initialization symbol for this MaterializationUnit (if any).
- const SymbolStringPtr &getInitializerSymbol() const { return InitSymbol; }
-
- /// Implementations of this method should materialize all symbols
- /// in the materialzation unit, except for those that have been
- /// previously discarded.
- virtual void
- materialize(std::unique_ptr<MaterializationResponsibility> R) = 0;
-
- /// Called by JITDylibs to notify MaterializationUnits that the given symbol
- /// has been overridden.
- void doDiscard(const JITDylib &JD, const SymbolStringPtr &Name) {
- SymbolFlags.erase(Name);
- if (InitSymbol == Name) {
- DEBUG_WITH_TYPE("orc", {
- dbgs() << "In " << getName() << ": discarding init symbol \""
- << *Name << "\"\n";
- });
- InitSymbol = nullptr;
- }
- discard(JD, std::move(Name));
- }
-
-protected:
- SymbolFlagsMap SymbolFlags;
- SymbolStringPtr InitSymbol;
-
-private:
- virtual void anchor();
-
- /// Implementations of this method should discard the given symbol
- /// from the source (e.g. if the source is an LLVM IR Module and the
- /// symbol is a function, delete the function body or mark it available
- /// externally).
- virtual void discard(const JITDylib &JD, const SymbolStringPtr &Name) = 0;
-};
-
/// A MaterializationUnit implementation for pre-existing absolute symbols.
///
/// All symbols will be resolved and marked ready as soon as the unit is
diff --git a/llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h b/llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h
new file mode 100644
index 00000000000000..115e5630f53a3d
--- /dev/null
+++ b/llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h
@@ -0,0 +1,105 @@
+//===---- MaterializationUnit.h -- Materialization Black Box ----*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// MaterializationUnit class and related types and operations.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_EXECUTIONENGINE_ORC_MATERIALIZATIONUNIT_H
+#define LLVM_EXECUTIONENGINE_ORC_MATERIALIZATIONUNIT_H
+
+#include "llvm/ADT/StringRef.h"
+#include "llvm/ExecutionEngine/Orc/CoreContainers.h"
+#include "llvm/ExecutionEngine/Orc/SymbolStringPool.h"
+
+namespace llvm {
+namespace orc {
+
+class MaterializationResponsibility;
+
+/// A MaterializationUnit represents a set of symbol definitions that can
+/// be materialized as a group, or individually discarded (when
+/// overriding definitions are encountered).
+///
+/// MaterializationUnits are used when providing lazy definitions of symbols to
+/// JITDylibs. The JITDylib will call materialize when the address of a symbol
+/// is requested via the lookup method. The JITDylib will call discard if a
+/// stronger definition is added or already present.
+class MaterializationUnit {
+ friend class ExecutionSession;
+ friend class JITDylib;
+
+public:
+ static char ID;
+
+ struct Interface {
+ Interface() = default;
+ Interface(SymbolFlagsMap InitalSymbolFlags, SymbolStringPtr InitSymbol)
+ : SymbolFlags(std::move(InitalSymbolFlags)),
+ InitSymbol(std::move(InitSymbol)) {
+ assert((!this->InitSymbol || this->SymbolFlags.count(this->InitSymbol)) &&
+ "If set, InitSymbol should appear in InitialSymbolFlags map");
+ }
+
+ SymbolFlagsMap SymbolFlags;
+ SymbolStringPtr InitSymbol;
+ };
+
+ MaterializationUnit(Interface I)
+ : SymbolFlags(std::move(I.SymbolFlags)),
+ InitSymbol(std::move(I.InitSymbol)) {}
+ virtual ~MaterializationUnit() = default;
+
+ /// Return the name of this materialization unit. Useful for debugging
+ /// output.
+ virtual StringRef getName() const = 0;
+
+ /// Return the set of symbols that this source provides.
+ const SymbolFlagsMap &getSymbols() const { return SymbolFlags; }
+
+ /// Returns the initialization symbol for this MaterializationUnit (if any).
+ const SymbolStringPtr &getInitializerSymbol() const { return InitSymbol; }
+
+ /// Implementations of this method should materialize all symbols
+ /// in the materialzation unit, except for those that have been
+ /// previously discarded.
+ virtual void
+ materialize(std::unique_ptr<MaterializationResponsibility> R) = 0;
+
+ /// Called by JITDylibs to notify MaterializationUnits that the given symbol
+ /// has been overridden.
+ void doDiscard(const JITDylib &JD, const SymbolStringPtr &Name) {
+ SymbolFlags.erase(Name);
+ if (InitSymbol == Name) {
+ DEBUG_WITH_TYPE("orc", {
+ dbgs() << "In " << getName() << ": discarding init symbol \""
+ << *Name << "\"\n";
+ });
+ InitSymbol = nullptr;
+ }
+ discard(JD, std::move(Name));
+ }
+
+protected:
+ SymbolFlagsMap SymbolFlags;
+ SymbolStringPtr InitSymbol;
+
+private:
+ virtual void anchor();
+
+ /// Implementations of this method should discard the given symbol
+ /// from the source (e.g. if the source is an LLVM IR Module and the
+ /// symbol is a function, delete the function body or mark it available
+ /// externally).
+ virtual void discard(const JITDylib &JD, const SymbolStringPtr &Name) = 0;
+};
+
+} // End namespace orc
+} // End namespace llvm
+
+#endif // LLVM_EXECUTIONENGINE_ORC_MATERIALIZATIONUNIT_H
>From 7085ac8a0718a3a37c7cb6641203e72fbc0b1aea Mon Sep 17 00:00:00 2001
From: Lang Hames <lhames at gmail.com>
Date: Sun, 10 Nov 2024 21:14:12 +1100
Subject: [PATCH 09/31] [ORC] Switch to C++17 nested namespaces. NFC.
---
llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h b/llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h
index 115e5630f53a3d..4ac8f6b6ba05ad 100644
--- a/llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h
+++ b/llvm/include/llvm/ExecutionEngine/Orc/MaterializationUnit.h
@@ -17,8 +17,7 @@
#include "llvm/ExecutionEngine/Orc/CoreContainers.h"
#include "llvm/ExecutionEngine/Orc/SymbolStringPool.h"
-namespace llvm {
-namespace orc {
+namespace llvm::orc {
class MaterializationResponsibility;
@@ -99,7 +98,6 @@ class MaterializationUnit {
virtual void discard(const JITDylib &JD, const SymbolStringPtr &Name) = 0;
};
-} // End namespace orc
-} // End namespace llvm
+} // namespace llvm::orc
#endif // LLVM_EXECUTIONENGINE_ORC_MATERIALIZATIONUNIT_H
>From ac30a0f349c960184c0165adcd87baecfc48a1af Mon Sep 17 00:00:00 2001
From: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: Sun, 10 Nov 2024 15:04:21 +0300
Subject: [PATCH 10/31] [PAC][lld] Do not emit warnings for `-z pac-plt` with
valid PAuth core info (#112959)
When PAuth core info is present and (platform,version) is not (0,0),
treat input files as pac-enabled and do not emit a warning with
`-z pac-plt` passed.
---
lld/ELF/Driver.cpp | 8 +++-
lld/test/ELF/aarch64-feature-pac.s | 2 +-
lld/test/ELF/aarch64-feature-pauth.s | 58 ++++++++++++++++++++++++++--
3 files changed, 62 insertions(+), 6 deletions(-)
diff --git a/lld/ELF/Driver.cpp b/lld/ELF/Driver.cpp
index ed93029721ecc1..fed6b21ddc5168 100644
--- a/lld/ELF/Driver.cpp
+++ b/lld/ELF/Driver.cpp
@@ -2792,6 +2792,8 @@ static void readSecurityNotes(Ctx &ctx) {
referenceFileName = (*it)->getName();
}
}
+ bool hasValidPauthAbiCoreInfo = llvm::any_of(
+ ctx.aarch64PauthAbiCoreInfo, [](uint8_t c) { return c != 0; });
for (ELFFileBase *f : ctx.objectFiles) {
uint32_t features = f->andFeatures;
@@ -2830,10 +2832,12 @@ static void readSecurityNotes(Ctx &ctx) {
"GNU_PROPERTY_X86_FEATURE_1_IBT property";
features |= GNU_PROPERTY_X86_FEATURE_1_IBT;
}
- if (ctx.arg.zPacPlt && !(features & GNU_PROPERTY_AARCH64_FEATURE_1_PAC)) {
+ if (ctx.arg.zPacPlt && !(hasValidPauthAbiCoreInfo ||
+ (features & GNU_PROPERTY_AARCH64_FEATURE_1_PAC))) {
Warn(ctx) << f
<< ": -z pac-plt: file does not have "
- "GNU_PROPERTY_AARCH64_FEATURE_1_PAC property";
+ "GNU_PROPERTY_AARCH64_FEATURE_1_PAC property and no valid "
+ "PAuth core info present for this link job";
features |= GNU_PROPERTY_AARCH64_FEATURE_1_PAC;
}
ctx.arg.andFeatures &= features;
diff --git a/lld/test/ELF/aarch64-feature-pac.s b/lld/test/ELF/aarch64-feature-pac.s
index b85a33216cb5bd..4fd1fd2acea737 100644
--- a/lld/test/ELF/aarch64-feature-pac.s
+++ b/lld/test/ELF/aarch64-feature-pac.s
@@ -82,7 +82,7 @@
# RUN: ld.lld %t.o %t2.o -z pac-plt %t.so -o %tpacplt.exe 2>&1 | FileCheck -DFILE=%t2.o --check-prefix WARN %s
-# WARN: warning: [[FILE]]: -z pac-plt: file does not have GNU_PROPERTY_AARCH64_FEATURE_1_PAC property
+# WARN: warning: [[FILE]]: -z pac-plt: file does not have GNU_PROPERTY_AARCH64_FEATURE_1_PAC property and no valid PAuth core info present for this link job
# RUN: llvm-readelf -n %tpacplt.exe | FileCheck --check-prefix=PACPROP %s
# RUN: llvm-readelf --dynamic-table %tpacplt.exe | FileCheck --check-prefix PACDYN2 %s
diff --git a/lld/test/ELF/aarch64-feature-pauth.s b/lld/test/ELF/aarch64-feature-pauth.s
index 699a650d72295a..3150c130d460f5 100644
--- a/lld/test/ELF/aarch64-feature-pauth.s
+++ b/lld/test/ELF/aarch64-feature-pauth.s
@@ -33,13 +33,53 @@
# RUN: llvm-mc -filetype=obj -triple=aarch64-linux-gnu no-info.s -o noinfo1.o
# RUN: cp noinfo1.o noinfo2.o
# RUN: not ld.lld -z pauth-report=error noinfo1.o tag1.o noinfo2.o -o /dev/null 2>&1 | FileCheck --check-prefix ERR5 %s
-# RUN: ld.lld -z pauth-report=warning noinfo1.o tag1.o noinfo2.o -o /dev/null 2>&1 | FileCheck --check-prefix WARN %s
+# RUN: ld.lld -z pauth-report=warning noinfo1.o tag1.o noinfo2.o -o /dev/null 2>&1 | FileCheck --check-prefix WARN1 %s
# RUN: ld.lld -z pauth-report=none noinfo1.o tag1.o noinfo2.o --fatal-warnings -o /dev/null
# ERR5: error: noinfo1.o: -z pauth-report: file does not have AArch64 PAuth core info while 'tag1.o' has one
# ERR5-NEXT: error: noinfo2.o: -z pauth-report: file does not have AArch64 PAuth core info while 'tag1.o' has one
-# WARN: warning: noinfo1.o: -z pauth-report: file does not have AArch64 PAuth core info while 'tag1.o' has one
-# WARN-NEXT: warning: noinfo2.o: -z pauth-report: file does not have AArch64 PAuth core info while 'tag1.o' has one
+# WARN1: warning: noinfo1.o: -z pauth-report: file does not have AArch64 PAuth core info while 'tag1.o' has one
+# WARN1-NEXT: warning: noinfo2.o: -z pauth-report: file does not have AArch64 PAuth core info while 'tag1.o' has one
+
+# RUN: llvm-mc -filetype=obj -triple=aarch64-linux-gnu abi-tag-zero.s -o tag-zero.o
+# RUN: llvm-mc -filetype=obj -triple=aarch64-linux-gnu %p/Inputs/aarch64-func2.s -o func2.o
+# RUN: llvm-mc -filetype=obj -triple=aarch64-linux-gnu %p/Inputs/aarch64-func3.s -o func3.o
+# RUN: ld.lld func3.o --shared -o func3.so
+# RUN: ld.lld tag1.o func2.o func3.so -z pac-plt --shared -o pacplt-nowarn --fatal-warnings
+# RUN: ld.lld tag-zero.o func2.o func3.so -z pac-plt --shared -o pacplt-warn 2>&1 | FileCheck --check-prefix WARN2 %s
+
+# WARN2: warning: tag-zero.o: -z pac-plt: file does not have GNU_PROPERTY_AARCH64_FEATURE_1_PAC property and no valid PAuth core info present for this link job
+# WARN2-NEXT: warning: func2.o: -z pac-plt: file does not have GNU_PROPERTY_AARCH64_FEATURE_1_PAC property and no valid PAuth core info present for this link job
+
+# RUN: llvm-readelf -d pacplt-nowarn | FileCheck --check-prefix=PACPLTTAG %s
+# RUN: llvm-readelf -d pacplt-warn | FileCheck --check-prefix=PACPLTTAG %s
+
+# PACPLTTAG: 0x0000000070000003 (AARCH64_PAC_PLT)
+
+# RUN: llvm-objdump -d pacplt-nowarn | FileCheck --check-prefix PACPLT -DA=10380 -DB=478 -DC=480 %s
+# RUN: llvm-objdump -d pacplt-warn | FileCheck --check-prefix PACPLT -DA=10390 -DB=488 -DC=490 %s
+
+# PACPLT: Disassembly of section .text:
+# PACPLT: <func2>:
+# PACPLT-NEXT: bl 0x[[A]] <func3 at plt>
+# PACPLT-NEXT: ret
+# PACPLT: Disassembly of section .plt:
+# PACPLT: <.plt>:
+# PACPLT-NEXT: stp x16, x30, [sp, #-0x10]!
+# PACPLT-NEXT: adrp x16, 0x30000 <func3+0x30000>
+# PACPLT-NEXT: ldr x17, [x16, #0x[[B]]]
+# PACPLT-NEXT: add x16, x16, #0x[[B]]
+# PACPLT-NEXT: br x17
+# PACPLT-NEXT: nop
+# PACPLT-NEXT: nop
+# PACPLT-NEXT: nop
+# PACPLT: <func3 at plt>:
+# PACPLT-NEXT: adrp x16, 0x30000 <func3+0x30000>
+# PACPLT-NEXT: ldr x17, [x16, #0x[[C]]]
+# PACPLT-NEXT: add x16, x16, #0x[[C]]
+# PACPLT-NEXT: autia1716
+# PACPLT-NEXT: br x17
+# PACPLT-NEXT: nop
#--- abi-tag-short.s
@@ -106,6 +146,18 @@
.quad 42 // platform
.quad 2 // version
+#--- abi-tag-zero.s
+
+.section ".note.gnu.property", "a"
+.long 4
+.long 24
+.long 5
+.asciz "GNU"
+.long 0xc0000001
+.long 16
+.quad 0 // platform
+.quad 0 // version
+
#--- no-info.s
## define _start to avoid missing entry warning and use --fatal-warnings to assert no diagnostic
>From 2c10664afafcd5915ebbde9cb7cb0e9cf8751b34 Mon Sep 17 00:00:00 2001
From: Nikolas Klauser <nikolasklauser at berlin.de>
Date: Sun, 10 Nov 2024 13:21:42 +0100
Subject: [PATCH 11/31] [libc++][NFC] Merge add_{const, cv, volatile}.h into a
single header (#115610)
There isn't much benefit in having granular headers for only a few
simple lines of code.
---
libcxx/include/CMakeLists.txt | 4 +--
libcxx/include/__type_traits/add_const.h | 32 -------------------
.../{add_cv.h => add_cv_quals.h} | 20 ++++++++++++
libcxx/include/__type_traits/add_volatile.h | 32 -------------------
.../__type_traits/is_trivially_assignable.h | 1 -
libcxx/include/__utility/as_const.h | 5 +--
libcxx/include/any | 2 +-
libcxx/include/module.modulemap | 4 +--
libcxx/include/type_traits | 4 +--
libcxx/include/variant | 4 +--
10 files changed, 26 insertions(+), 82 deletions(-)
delete mode 100644 libcxx/include/__type_traits/add_const.h
rename libcxx/include/__type_traits/{add_cv.h => add_cv_quals.h} (66%)
delete mode 100644 libcxx/include/__type_traits/add_volatile.h
diff --git a/libcxx/include/CMakeLists.txt b/libcxx/include/CMakeLists.txt
index ae2e8bcb32aaa4..938d0bb872e0b5 100644
--- a/libcxx/include/CMakeLists.txt
+++ b/libcxx/include/CMakeLists.txt
@@ -738,12 +738,10 @@ set(files
__tuple/tuple_like_no_subrange.h
__tuple/tuple_size.h
__tuple/tuple_types.h
- __type_traits/add_const.h
- __type_traits/add_cv.h
+ __type_traits/add_cv_quals.h
__type_traits/add_lvalue_reference.h
__type_traits/add_pointer.h
__type_traits/add_rvalue_reference.h
- __type_traits/add_volatile.h
__type_traits/aligned_storage.h
__type_traits/aligned_union.h
__type_traits/alignment_of.h
diff --git a/libcxx/include/__type_traits/add_const.h b/libcxx/include/__type_traits/add_const.h
deleted file mode 100644
index 9a6f1c10299f7f..00000000000000
--- a/libcxx/include/__type_traits/add_const.h
+++ /dev/null
@@ -1,32 +0,0 @@
-//===----------------------------------------------------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef _LIBCPP___TYPE_TRAITS_ADD_CONST_H
-#define _LIBCPP___TYPE_TRAITS_ADD_CONST_H
-
-#include <__config>
-
-#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER)
-# pragma GCC system_header
-#endif
-
-_LIBCPP_BEGIN_NAMESPACE_STD
-
-template <class _Tp>
-struct _LIBCPP_TEMPLATE_VIS add_const {
- typedef _LIBCPP_NODEBUG const _Tp type;
-};
-
-#if _LIBCPP_STD_VER >= 14
-template <class _Tp>
-using add_const_t = typename add_const<_Tp>::type;
-#endif
-
-_LIBCPP_END_NAMESPACE_STD
-
-#endif // _LIBCPP___TYPE_TRAITS_ADD_CONST_H
diff --git a/libcxx/include/__type_traits/add_cv.h b/libcxx/include/__type_traits/add_cv_quals.h
similarity index 66%
rename from libcxx/include/__type_traits/add_cv.h
rename to libcxx/include/__type_traits/add_cv_quals.h
index 9e23e5ceb7a3bd..1d35b89f42c2d1 100644
--- a/libcxx/include/__type_traits/add_cv.h
+++ b/libcxx/include/__type_traits/add_cv_quals.h
@@ -17,6 +17,16 @@
_LIBCPP_BEGIN_NAMESPACE_STD
+template <class _Tp>
+struct _LIBCPP_TEMPLATE_VIS add_const {
+ typedef _LIBCPP_NODEBUG const _Tp type;
+};
+
+#if _LIBCPP_STD_VER >= 14
+template <class _Tp>
+using add_const_t = typename add_const<_Tp>::type;
+#endif
+
template <class _Tp>
struct _LIBCPP_TEMPLATE_VIS add_cv {
typedef _LIBCPP_NODEBUG const volatile _Tp type;
@@ -27,6 +37,16 @@ template <class _Tp>
using add_cv_t = typename add_cv<_Tp>::type;
#endif
+template <class _Tp>
+struct _LIBCPP_TEMPLATE_VIS add_volatile {
+ typedef _LIBCPP_NODEBUG volatile _Tp type;
+};
+
+#if _LIBCPP_STD_VER >= 14
+template <class _Tp>
+using add_volatile_t = typename add_volatile<_Tp>::type;
+#endif
+
_LIBCPP_END_NAMESPACE_STD
#endif // _LIBCPP___TYPE_TRAITS_ADD_CV_H
diff --git a/libcxx/include/__type_traits/add_volatile.h b/libcxx/include/__type_traits/add_volatile.h
deleted file mode 100644
index 56b7dfaac026e7..00000000000000
--- a/libcxx/include/__type_traits/add_volatile.h
+++ /dev/null
@@ -1,32 +0,0 @@
-//===----------------------------------------------------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef _LIBCPP___TYPE_TRAITS_ADD_VOLATILE_H
-#define _LIBCPP___TYPE_TRAITS_ADD_VOLATILE_H
-
-#include <__config>
-
-#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER)
-# pragma GCC system_header
-#endif
-
-_LIBCPP_BEGIN_NAMESPACE_STD
-
-template <class _Tp>
-struct _LIBCPP_TEMPLATE_VIS add_volatile {
- typedef _LIBCPP_NODEBUG volatile _Tp type;
-};
-
-#if _LIBCPP_STD_VER >= 14
-template <class _Tp>
-using add_volatile_t = typename add_volatile<_Tp>::type;
-#endif
-
-_LIBCPP_END_NAMESPACE_STD
-
-#endif // _LIBCPP___TYPE_TRAITS_ADD_VOLATILE_H
diff --git a/libcxx/include/__type_traits/is_trivially_assignable.h b/libcxx/include/__type_traits/is_trivially_assignable.h
index 201333b0fa0b33..7720c3e637506a 100644
--- a/libcxx/include/__type_traits/is_trivially_assignable.h
+++ b/libcxx/include/__type_traits/is_trivially_assignable.h
@@ -10,7 +10,6 @@
#define _LIBCPP___TYPE_TRAITS_IS_TRIVIALLY_ASSIGNABLE_H
#include <__config>
-#include <__type_traits/add_const.h>
#include <__type_traits/add_lvalue_reference.h>
#include <__type_traits/add_rvalue_reference.h>
#include <__type_traits/integral_constant.h>
diff --git a/libcxx/include/__utility/as_const.h b/libcxx/include/__utility/as_const.h
index 582dd42f407915..0f54b984725c60 100644
--- a/libcxx/include/__utility/as_const.h
+++ b/libcxx/include/__utility/as_const.h
@@ -10,9 +10,6 @@
#define _LIBCPP___UTILITY_AS_CONST_H
#include <__config>
-#include <__type_traits/add_const.h>
-#include <__utility/forward.h>
-#include <__utility/move.h>
#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER)
# pragma GCC system_header
@@ -22,7 +19,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD
#if _LIBCPP_STD_VER >= 17
template <class _Tp>
-[[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr add_const_t<_Tp>& as_const(_Tp& __t) noexcept {
+[[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr const _Tp& as_const(_Tp& __t) noexcept {
return __t;
}
diff --git a/libcxx/include/any b/libcxx/include/any
index e32aa7f8e8a420..719dc2cf999e50 100644
--- a/libcxx/include/any
+++ b/libcxx/include/any
@@ -85,7 +85,7 @@ namespace std {
#include <__memory/allocator_destructor.h>
#include <__memory/allocator_traits.h>
#include <__memory/unique_ptr.h>
-#include <__type_traits/add_const.h>
+#include <__type_traits/add_cv_quals.h>
#include <__type_traits/add_pointer.h>
#include <__type_traits/aligned_storage.h>
#include <__type_traits/conditional.h>
diff --git a/libcxx/include/module.modulemap b/libcxx/include/module.modulemap
index 6b0cc07fca0787..5465d603b2c4d0 100644
--- a/libcxx/include/module.modulemap
+++ b/libcxx/include/module.modulemap
@@ -63,12 +63,10 @@ module std_core [system] {
}
module type_traits {
- module add_const { header "__type_traits/add_const.h" }
- module add_cv { header "__type_traits/add_cv.h" }
+ module add_cv_quals { header "__type_traits/add_cv_quals.h" }
module add_lvalue_reference { header "__type_traits/add_lvalue_reference.h" }
module add_pointer { header "__type_traits/add_pointer.h" }
module add_rvalue_reference { header "__type_traits/add_rvalue_reference.h" }
- module add_volatile { header "__type_traits/add_volatile.h" }
module aligned_storage { header "__type_traits/aligned_storage.h" }
module aligned_union { header "__type_traits/aligned_union.h" }
module alignment_of { header "__type_traits/alignment_of.h" }
diff --git a/libcxx/include/type_traits b/libcxx/include/type_traits
index baeed35ca8508b..cc2b7511d24d3b 100644
--- a/libcxx/include/type_traits
+++ b/libcxx/include/type_traits
@@ -425,12 +425,10 @@ namespace std
*/
#include <__config>
-#include <__type_traits/add_const.h>
-#include <__type_traits/add_cv.h>
+#include <__type_traits/add_cv_quals.h>
#include <__type_traits/add_lvalue_reference.h>
#include <__type_traits/add_pointer.h>
#include <__type_traits/add_rvalue_reference.h>
-#include <__type_traits/add_volatile.h>
#include <__type_traits/aligned_storage.h>
#include <__type_traits/aligned_union.h>
#include <__type_traits/alignment_of.h>
diff --git a/libcxx/include/variant b/libcxx/include/variant
index 6e752556a888dd..f604527cd22569 100644
--- a/libcxx/include/variant
+++ b/libcxx/include/variant
@@ -226,10 +226,8 @@ namespace std {
#include <__memory/construct_at.h>
#include <__tuple/find_index.h>
#include <__tuple/sfinae_helpers.h>
-#include <__type_traits/add_const.h>
-#include <__type_traits/add_cv.h>
+#include <__type_traits/add_cv_quals.h>
#include <__type_traits/add_pointer.h>
-#include <__type_traits/add_volatile.h>
#include <__type_traits/common_type.h>
#include <__type_traits/conditional.h>
#include <__type_traits/conjunction.h>
>From ad2d313f7455fe27896db8df9ea9aadd60b53436 Mon Sep 17 00:00:00 2001
From: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: Sun, 10 Nov 2024 12:22:25 +0000
Subject: [PATCH 12/31] [gn build] Port 2c10664afafc
---
llvm/utils/gn/secondary/libcxx/include/BUILD.gn | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
index dc62280d12c666..13a3a15b858775 100644
--- a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
+++ b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn
@@ -810,12 +810,10 @@ if (current_toolchain == default_toolchain) {
"__tuple/tuple_like_no_subrange.h",
"__tuple/tuple_size.h",
"__tuple/tuple_types.h",
- "__type_traits/add_const.h",
- "__type_traits/add_cv.h",
+ "__type_traits/add_cv_quals.h",
"__type_traits/add_lvalue_reference.h",
"__type_traits/add_pointer.h",
"__type_traits/add_rvalue_reference.h",
- "__type_traits/add_volatile.h",
"__type_traits/aligned_storage.h",
"__type_traits/aligned_union.h",
"__type_traits/alignment_of.h",
>From 7c13477351046c115ad86e047f3f7346bb925b19 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Sun, 10 Nov 2024 15:48:13 +0300
Subject: [PATCH 13/31] [X86] Delete unused X86setcc_commute node (NFC)
(#115650)
The last use was removed by 87aa59a0.
---
llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 3 ---
1 file changed, 3 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
index c09522709d2f0d..f6231b78f4c2e8 100644
--- a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+++ b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
@@ -1450,9 +1450,6 @@ def X86Vpshufbitqmb_su : PatFrag<(ops node:$src1, node:$src2),
return N->hasOneUse();
}]>;
-// This fragment treats X86cmpm as commutable to help match loads in both
-// operands for PCMPEQ.
-def X86setcc_commute : SDNode<"ISD::SETCC", SDTSetCC, [SDNPCommutative]>;
def X86pcmpgtm : PatFrag<(ops node:$src1, node:$src2),
(setcc node:$src1, node:$src2, SETGT)>;
>From 99f1019f596f745c720e97137bcadb239c573e3e Mon Sep 17 00:00:00 2001
From: MarcoFalke <*~=`'#}+{/-|&$^_ at 721217.xyz>
Date: Sun, 10 Nov 2024 15:30:23 +0100
Subject: [PATCH 14/31] [NFC] Trivial doc fixup in SafeBuffers.rst
---
clang/docs/SafeBuffers.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/docs/SafeBuffers.rst b/clang/docs/SafeBuffers.rst
index 144c3a76a5832f..da75907e174a00 100644
--- a/clang/docs/SafeBuffers.rst
+++ b/clang/docs/SafeBuffers.rst
@@ -58,7 +58,7 @@ A relatively fresh version of C++ is recommended. In particular, the very useful
standard view class ``std::span`` requires C++20.
Other implementations of the C++ standard library may provide different
-flags to enable such hardening hardening.
+flags to enable such hardening.
If you're using custom containers and views, they will need to be hardened
this way as well, but you don't necessarily need to do this ahead of time.
>From 1d6d073fbbaebbde6891501fe20f02a0ea345131 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Sun, 10 Nov 2024 14:51:55 +0000
Subject: [PATCH 15/31] [AArch64] Remove FeatureUseScalarIncVL
FeatureUseScalarIncVL is a tuning feature, used to control whether addvl or
add+cnt is used. It was previously added as a dependency for FeatureSVE2, an
architecture feature but this can be seen as a layering violation. The main
disadvantage is that -use-scalar-inc-vl cannot be used without disabling sve2
and all dependant features.
This patch now replaces that with an option that if unset defaults to hasSVE ||
hasSME, but is otherwise overriden by the option. The hope is that no cpus will
rely on the tuning feature (or we can readdit if needed.
---
llvm/lib/Target/AArch64/AArch64Features.td | 7 ++-----
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 12 ++++++++++++
llvm/lib/Target/AArch64/AArch64Subtarget.h | 4 ++++
.../AArch64/sve-intrinsics-counting-elems-i32.ll | 2 +-
.../CodeGen/AArch64/sve-intrinsics-counting-elems.ll | 4 +++-
llvm/test/CodeGen/AArch64/sve-vl-arith.ll | 3 ++-
6 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 6d8554cf1884c1..a2349079889175 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -358,12 +358,9 @@ def FeatureTHE : ExtensionWithMArch<"the", "THE", "FEAT_THE",
// Armv9.0 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl",
- "UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">;
-
def FeatureSVE2 : ExtensionWithMArch<"sve2", "SVE2", "FEAT_SVE2",
"Enable Scalable Vector Extension 2 (SVE2) instructions",
- [FeatureSVE, FeatureUseScalarIncVL]>;
+ [FeatureSVE]>;
def FeatureSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES",
"FEAT_SVE_AES, FEAT_SVE_PMULL128",
@@ -403,7 +400,7 @@ def FeatureRME : Extension<"rme", "RME", "FEAT_RME",
"Enable Realm Management Extension">;
def FeatureSME : ExtensionWithMArch<"sme", "SME", "FEAT_SME",
- "Enable Scalable Matrix Extension (SME)", [FeatureBF16, FeatureUseScalarIncVL]>;
+ "Enable Scalable Matrix Extension (SME)", [FeatureBF16]>;
def FeatureSMEF64F64 : ExtensionWithMArch<"sme-f64f64", "SMEF64F64", "FEAT_SME_F64F64",
"Enable Scalable Matrix Extension (SME) F64F64 instructions", [FeatureSME]>;
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index 736d57e6ae2fd9..bc11b2e06cf1c1 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -93,6 +93,10 @@ static cl::opt<bool>
cl::init(false), cl::Hidden,
cl::desc("Enable subreg liveness tracking"));
+static cl::opt<bool>
+ UseScalarIncVL("sve-use-scalar-inc-vl", cl::init(false), cl::Hidden,
+ cl::desc("Prefer add+cnt over addvl/inc/dec"));
+
unsigned AArch64Subtarget::getVectorInsertExtractBaseCost() const {
if (OverrideVectorInsertExtractBaseCost.getNumOccurrences() > 0)
return OverrideVectorInsertExtractBaseCost;
@@ -575,6 +579,14 @@ void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {
bool AArch64Subtarget::useAA() const { return UseAA; }
+bool AArch64Subtarget::useScalarIncVL() const {
+ // If SVE2 or SME is present (we are not SVE-1 only) and UseScalarIncVL
+ // is not otherwise set, enable it by default.
+ if (UseScalarIncVL.getNumOccurrences())
+ return UseScalarIncVL;
+ return hasSVE2() || hasSME();
+}
+
// If return address signing is enabled, tail calls are emitted as follows:
//
// ```
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index f3dcce3f3994ba..7f5883289c6ddd 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -417,6 +417,10 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
return DefaultSVETFOpts;
}
+ /// Returns true to use the addvl/inc/dec instructions, as opposed to separate
+ /// add + cnt instructions.
+ bool useScalarIncVL() const;
+
const char* getChkStkName() const {
if (isWindowsArm64EC())
return "#__chkstk_arm64ec";
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
index 5062a43da931f8..02d172fbc9dbfd 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s -check-prefix=NO_SCALAR_INC
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+use-scalar-inc-vl < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -sve-use-scalar-inc-vl=true < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
; INCB
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
index 8f0a9eac87c27c..4e1ff4abd6ffdf 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
@@ -1,8 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+use-scalar-inc-vl < %s | FileCheck %s -check-prefix=USE_SCALAR_INC
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -sve-use-scalar-inc-vl=true < %s | FileCheck %s -check-prefix=USE_SCALAR_INC
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s -check-prefix=USE_SCALAR_INC
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s -check-prefix=USE_SCALAR_INC
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -sve-use-scalar-inc-vl=false < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -sve-use-scalar-inc-vl=false -force-streaming < %s | FileCheck %s
;
; CNTB
diff --git a/llvm/test/CodeGen/AArch64/sve-vl-arith.ll b/llvm/test/CodeGen/AArch64/sve-vl-arith.ll
index de2af590acd1e2..dad357c8a0c132 100644
--- a/llvm/test/CodeGen/AArch64/sve-vl-arith.ll
+++ b/llvm/test/CodeGen/AArch64/sve-vl-arith.ll
@@ -1,7 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -verify-machineinstrs < %s | FileCheck %s -check-prefix=NO_SCALAR_INC
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+use-scalar-inc-vl -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -sve-use-scalar-inc-vl=true -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -sve-use-scalar-inc-vl=false -verify-machineinstrs < %s | FileCheck %s -check-prefix=NO_SCALAR_INC
define <vscale x 8 x i16> @inch_vec(<vscale x 8 x i16> %a) {
; NO_SCALAR_INC-LABEL: inch_vec:
>From c8f33738a5a801b5bc083ae9b2ced39ef1b12980 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Sun, 10 Nov 2024 15:03:01 +0000
Subject: [PATCH 16/31] [AArch64] Rewrite arm64-ext.ll test and cleanup. NFC
---
llvm/test/CodeGen/AArch64/arm64-ext.ll | 165 ++++++++++++++-----------
1 file changed, 92 insertions(+), 73 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/arm64-ext.ll b/llvm/test/CodeGen/AArch64/arm64-ext.ll
index c38ab076e4ea53..8bb6aebe1e8281 100644
--- a/llvm/test/CodeGen/AArch64/arm64-ext.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-ext.ll
@@ -1,92 +1,100 @@
-; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=arm64-eabi -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-define <8 x i8> @test_vextd(ptr %A, ptr %B) nounwind {
-;CHECK-LABEL: test_vextd:
-;CHECK: {{ext.8b.*#3}}
- %tmp1 = load <8 x i8>, ptr %A
- %tmp2 = load <8 x i8>, ptr %B
- %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
- ret <8 x i8> %tmp3
+define <8 x i8> @test_vextd(<8 x i8> %tmp1, <8 x i8> %tmp2) {
+; CHECK-LABEL: test_vextd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #3
+; CHECK-NEXT: ret
+ %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
+ ret <8 x i8> %tmp3
}
-define <8 x i8> @test_vextRd(ptr %A, ptr %B) nounwind {
-;CHECK-LABEL: test_vextRd:
-;CHECK: {{ext.8b.*#5}}
- %tmp1 = load <8 x i8>, ptr %A
- %tmp2 = load <8 x i8>, ptr %B
- %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4>
- ret <8 x i8> %tmp3
+define <8 x i8> @test_vextRd(<8 x i8> %tmp1, <8 x i8> %tmp2) {
+; CHECK-LABEL: test_vextRd:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #5
+; CHECK-NEXT: ret
+ %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4>
+ ret <8 x i8> %tmp3
}
-define <16 x i8> @test_vextq(ptr %A, ptr %B) nounwind {
-;CHECK-LABEL: test_vextq:
-;CHECK: {{ext.16b.*3}}
- %tmp1 = load <16 x i8>, ptr %A
- %tmp2 = load <16 x i8>, ptr %B
- %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>
- ret <16 x i8> %tmp3
+define <16 x i8> @test_vextq(<16 x i8> %tmp1, <16 x i8> %tmp2) {
+; CHECK-LABEL: test_vextq:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #3
+; CHECK-NEXT: ret
+ %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>
+ ret <16 x i8> %tmp3
}
-define <16 x i8> @test_vextRq(ptr %A, ptr %B) nounwind {
-;CHECK-LABEL: test_vextRq:
-;CHECK: {{ext.16b.*7}}
- %tmp1 = load <16 x i8>, ptr %A
- %tmp2 = load <16 x i8>, ptr %B
- %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
- ret <16 x i8> %tmp3
+define <16 x i8> @test_vextRq(<16 x i8> %tmp1, <16 x i8> %tmp2) {
+; CHECK-LABEL: test_vextRq:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v0.16b, v1.16b, v0.16b, #7
+; CHECK-NEXT: ret
+ %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
+ ret <16 x i8> %tmp3
}
-define <4 x i16> @test_vextd16(ptr %A, ptr %B) nounwind {
-;CHECK-LABEL: test_vextd16:
-;CHECK: {{ext.8b.*#6}}
- %tmp1 = load <4 x i16>, ptr %A
- %tmp2 = load <4 x i16>, ptr %B
- %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
- ret <4 x i16> %tmp3
+define <4 x i16> @test_vextd16(<4 x i16> %tmp1, <4 x i16> %tmp2) {
+; CHECK-LABEL: test_vextd16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #6
+; CHECK-NEXT: ret
+ %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
+ ret <4 x i16> %tmp3
}
-define <4 x i32> @test_vextq32(ptr %A, ptr %B) nounwind {
-;CHECK-LABEL: test_vextq32:
-;CHECK: {{ext.16b.*12}}
- %tmp1 = load <4 x i32>, ptr %A
- %tmp2 = load <4 x i32>, ptr %B
- %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
- ret <4 x i32> %tmp3
+define <4 x i32> @test_vextq32(<4 x i32> %tmp1, <4 x i32> %tmp2) {
+; CHECK-LABEL: test_vextq32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #12
+; CHECK-NEXT: ret
+ %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
+ ret <4 x i32> %tmp3
}
; Undef shuffle indices should not prevent matching to VEXT:
-define <8 x i8> @test_vextd_undef(ptr %A, ptr %B) nounwind {
-;CHECK-LABEL: test_vextd_undef:
-;CHECK: {{ext.8b.*}}
- %tmp1 = load <8 x i8>, ptr %A
- %tmp2 = load <8 x i8>, ptr %B
- %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10>
- ret <8 x i8> %tmp3
+define <8 x i8> @test_vextd_undef(<8 x i8> %tmp1, <8 x i8> %tmp2) {
+; CHECK-LABEL: test_vextd_undef:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #3
+; CHECK-NEXT: ret
+ %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10>
+ ret <8 x i8> %tmp3
}
-define <8 x i8> @test_vextd_undef2(ptr %A, ptr %B) nounwind {
-;CHECK-LABEL: test_vextd_undef2:
-;CHECK: {{ext.8b.*#6}}
- %tmp1 = load <8 x i8>, ptr %A
- %tmp2 = load <8 x i8>, ptr %B
+define <8 x i8> @test_vextd_undef2(<8 x i8> %tmp1, <8 x i8> %tmp2) {
+; CHECK-SD-LABEL: test_vextd_undef2:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v0.8b, v0.8b, v0.8b, #6
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vextd_undef2:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ext v0.8b, v1.8b, v0.8b, #6
+; CHECK-GI-NEXT: ret
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 3, i32 4, i32 5>
ret <8 x i8> %tmp3
}
-define <16 x i8> @test_vextRq_undef(ptr %A, ptr %B) nounwind {
-;CHECK-LABEL: test_vextRq_undef:
-;CHECK: {{ext.16b.*#7}}
- %tmp1 = load <16 x i8>, ptr %A
- %tmp2 = load <16 x i8>, ptr %B
- %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 undef, i32 undef, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 undef, i32 6>
- ret <16 x i8> %tmp3
+define <16 x i8> @test_vextRq_undef(<16 x i8> %tmp1, <16 x i8> %tmp2) {
+; CHECK-LABEL: test_vextRq_undef:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v0.16b, v1.16b, v0.16b, #7
+; CHECK-NEXT: ret
+ %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 undef, i32 undef, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 undef, i32 6>
+ ret <16 x i8> %tmp3
}
-define <8 x i16> @test_vextRq_undef2(ptr %A) nounwind {
-;CHECK-LABEL: test_vextRq_undef2:
-;CHECK: {{ext.16b.*#10}}
- %tmp1 = load <8 x i16>, ptr %A
+define <8 x i16> @test_vextRq_undef2(<8 x i16> %tmp1) nounwind {
+; CHECK-LABEL: test_vextRq_undef2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #10
+; CHECK-NEXT: ret
%vext = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2, i32 3, i32 4>
ret <8 x i16> %vext;
}
@@ -95,11 +103,22 @@ define <8 x i16> @test_vextRq_undef2(ptr %A) nounwind {
; chosen to reach lowering phase as a BUILD_VECTOR.
; An undef in the shuffle list should still be optimizable
-define <4 x i16> @test_undef(ptr %A, ptr %B) nounwind {
-;CHECK-LABEL: test_undef:
-;CHECK: zip1.4h
- %tmp1 = load <8 x i16>, ptr %A
- %tmp2 = load <8 x i16>, ptr %B
- %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 undef, i32 8, i32 5, i32 9>
- ret <4 x i16> %tmp3
+define <4 x i16> @test_undef(<8 x i16> %tmp1, <8 x i16> %tmp2) {
+; CHECK-SD-LABEL: test_undef:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: zip1 v0.4h, v0.4h, v1.4h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_undef:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI10_0
+; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI10_0]
+; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
+ %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 undef, i32 8, i32 5, i32 9>
+ ret <4 x i16> %tmp3
}
>From 91a48e06463b23679907e151bdfec3e6093e9f16 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Sun, 10 Nov 2024 15:19:31 +0000
Subject: [PATCH 17/31] [AArch64][GlobalISel] Implicitly truncate APInt in
matchExt combine.
The APInt using FirstRealElt + 1 is intended to match the next element, which
might overflow the size of MaskBits. This prevents a new assert in APInt from
triggering.
---
.../AArch64/GISel/AArch64PostLegalizerLowering.cpp | 2 +-
llvm/test/CodeGen/AArch64/arm64-ext.ll | 9 +++++++++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 2bcfdc1b46873b..41bd21779fe319 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -90,7 +90,7 @@ std::optional<std::pair<bool, uint64_t>> getExtMask(ArrayRef<int> M,
// Use APInt to handle overflow when calculating expected element.
unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
- APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
+ APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1, false, true);
// The following shuffle indices must be the successive elements after the
// first real element.
diff --git a/llvm/test/CodeGen/AArch64/arm64-ext.ll b/llvm/test/CodeGen/AArch64/arm64-ext.ll
index 8bb6aebe1e8281..a74972deb5552d 100644
--- a/llvm/test/CodeGen/AArch64/arm64-ext.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-ext.ll
@@ -122,3 +122,12 @@ define <4 x i16> @test_undef(<8 x i16> %tmp1, <8 x i16> %tmp2) {
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 undef, i32 8, i32 5, i32 9>
ret <4 x i16> %tmp3
}
+
+define <2 x i64> @test_v2s64(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: test_v2s64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v0.16b, v1.16b, v0.16b, #8
+; CHECK-NEXT: ret
+ %s = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 3, i32 0>
+ ret <2 x i64> %s
+}
>From 5b19ed8bb4a36bd0b96f18151932aebd7a67f0e1 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu at google.com>
Date: Sun, 10 Nov 2024 07:24:06 -0800
Subject: [PATCH 18/31] [llvm] Migrate away from
PointerUnion::{is,get,dyn_cast} (NFC) (#115626)
Note that PointerUnion::{is,get,dyn_cast} have been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
---
llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp | 6 +++---
llvm/lib/CodeGen/GlobalISel/Utils.cpp | 4 ++--
llvm/lib/IR/DIBuilder.cpp | 4 ++--
llvm/lib/IR/DebugInfo.cpp | 6 +++---
llvm/lib/IR/Metadata.cpp | 10 +++++-----
llvm/lib/SandboxIR/Tracker.cpp | 12 ++++++------
llvm/lib/Transforms/Scalar/SROA.cpp | 8 +++-----
llvm/lib/Transforms/Utils/Local.cpp | 4 ++--
8 files changed, 26 insertions(+), 28 deletions(-)
diff --git a/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp b/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
index 59257fd6aadd52..a465f52bfd5936 100644
--- a/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
+++ b/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp
@@ -1051,10 +1051,10 @@ class AssignmentTrackingLowering {
OS << ", s=";
if (Source.isNull())
OS << "null";
- else if (isa<DbgAssignIntrinsic *>(Source))
- OS << Source.get<DbgAssignIntrinsic *>();
+ else if (const auto *DAI = dyn_cast<DbgAssignIntrinsic *>(Source))
+ OS << DAI;
else
- OS << Source.get<DbgVariableRecord *>();
+ OS << cast<DbgVariableRecord *>(Source);
OS << ")";
}
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index 5cee07461d7e22..45807a6818ee5e 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -214,8 +214,8 @@ bool llvm::canReplaceReg(Register DstReg, Register SrcReg,
// Otherwise match if the Src is already a regclass that is covered by the Dst
// RegBank.
- return DstRBC.is<const RegisterBank *>() && MRI.getRegClassOrNull(SrcReg) &&
- DstRBC.get<const RegisterBank *>()->covers(
+ return isa<const RegisterBank *>(DstRBC) && MRI.getRegClassOrNull(SrcReg) &&
+ cast<const RegisterBank *>(DstRBC)->covers(
*MRI.getRegClassOrNull(SrcReg));
}
diff --git a/llvm/lib/IR/DIBuilder.cpp b/llvm/lib/IR/DIBuilder.cpp
index 665eda28c7d871..3d8e12e95b774f 100644
--- a/llvm/lib/IR/DIBuilder.cpp
+++ b/llvm/lib/IR/DIBuilder.cpp
@@ -1033,8 +1033,8 @@ DbgInstPtr DIBuilder::insertDbgValueIntrinsic(Value *V,
DbgInstPtr DVI = insertDbgValueIntrinsic(
V, VarInfo, Expr, DL, InsertBefore ? InsertBefore->getParent() : nullptr,
InsertBefore);
- if (DVI.is<Instruction *>())
- cast<CallInst>(DVI.get<Instruction *>())->setTailCall();
+ if (auto *Inst = dyn_cast<Instruction *>(DVI))
+ cast<CallInst>(Inst)->setTailCall();
return DVI;
}
diff --git a/llvm/lib/IR/DebugInfo.cpp b/llvm/lib/IR/DebugInfo.cpp
index e20a0f053481ed..e5b45e0082a823 100644
--- a/llvm/lib/IR/DebugInfo.cpp
+++ b/llvm/lib/IR/DebugInfo.cpp
@@ -2099,10 +2099,10 @@ static void emitDbgAssign(AssignmentInfo Info, Value *Val, Value *Dest,
AddrExpr, VarRec.DL);
(void)Assign;
LLVM_DEBUG(if (!Assign.isNull()) {
- if (Assign.is<DbgRecord *>())
- errs() << " > INSERT: " << *Assign.get<DbgRecord *>() << "\n";
+ if (const auto *Record = dyn_cast<DbgRecord *>(Assign))
+ errs() << " > INSERT: " << *Record << "\n";
else
- errs() << " > INSERT: " << *Assign.get<Instruction *>() << "\n";
+ errs() << " > INSERT: " << *cast<Instruction *>(Assign) << "\n";
});
}
diff --git a/llvm/lib/IR/Metadata.cpp b/llvm/lib/IR/Metadata.cpp
index 28f2ca550f5ec9..98cfbd11fde58f 100644
--- a/llvm/lib/IR/Metadata.cpp
+++ b/llvm/lib/IR/Metadata.cpp
@@ -274,7 +274,7 @@ ReplaceableMetadataImpl::getAllDbgVariableRecordUsers() {
OwnerTy Owner = Pair.second.first;
if (Owner.isNull())
continue;
- if (!Owner.is<DebugValueUser *>())
+ if (!isa<DebugValueUser *>(Owner))
continue;
DVRUsersWithID.push_back(&UseMap[Pair.first]);
}
@@ -288,7 +288,7 @@ ReplaceableMetadataImpl::getAllDbgVariableRecordUsers() {
});
SmallVector<DbgVariableRecord *> DVRUsers;
for (auto UserWithID : DVRUsersWithID)
- DVRUsers.push_back(UserWithID->first.get<DebugValueUser *>()->getUser());
+ DVRUsers.push_back(cast<DebugValueUser *>(UserWithID->first)->getUser());
return DVRUsers;
}
@@ -396,8 +396,8 @@ void ReplaceableMetadataImpl::replaceAllUsesWith(Metadata *MD) {
continue;
}
- if (Owner.is<DebugValueUser *>()) {
- Owner.get<DebugValueUser *>()->handleChangedValue(Pair.first, MD);
+ if (auto *DVU = dyn_cast<DebugValueUser *>(Owner)) {
+ DVU->handleChangedValue(Pair.first, MD);
continue;
}
@@ -436,7 +436,7 @@ void ReplaceableMetadataImpl::resolveAllUses(bool ResolveUsers) {
auto Owner = Pair.second.first;
if (!Owner)
continue;
- if (!Owner.is<Metadata *>())
+ if (!isa<Metadata *>(Owner))
continue;
// Resolve MDNodes that point at this.
diff --git a/llvm/lib/SandboxIR/Tracker.cpp b/llvm/lib/SandboxIR/Tracker.cpp
index abcad39330094d..e4f84dee07e4da 100644
--- a/llvm/lib/SandboxIR/Tracker.cpp
+++ b/llvm/lib/SandboxIR/Tracker.cpp
@@ -111,10 +111,10 @@ void EraseFromParent::accept() {
void EraseFromParent::revert(Tracker &Tracker) {
// Place the bottom-most instruction first.
auto [Operands, BotLLVMI] = InstrData[0];
- if (auto *NextLLVMI = NextLLVMIOrBB.dyn_cast<llvm::Instruction *>()) {
+ if (auto *NextLLVMI = dyn_cast<llvm::Instruction *>(NextLLVMIOrBB)) {
BotLLVMI->insertBefore(NextLLVMI);
} else {
- auto *LLVMBB = NextLLVMIOrBB.get<llvm::BasicBlock *>();
+ auto *LLVMBB = cast<llvm::BasicBlock *>(NextLLVMIOrBB);
BotLLVMI->insertInto(LLVMBB, LLVMBB->end());
}
for (auto [OpNum, Op] : enumerate(Operands))
@@ -145,10 +145,10 @@ RemoveFromParent::RemoveFromParent(Instruction *RemovedI) : RemovedI(RemovedI) {
}
void RemoveFromParent::revert(Tracker &Tracker) {
- if (auto *NextI = NextInstrOrBB.dyn_cast<Instruction *>()) {
+ if (auto *NextI = dyn_cast<Instruction *>(NextInstrOrBB)) {
RemovedI->insertBefore(NextI);
} else {
- auto *BB = NextInstrOrBB.get<BasicBlock *>();
+ auto *BB = cast<BasicBlock *>(NextInstrOrBB);
RemovedI->insertInto(BB, BB->end());
}
}
@@ -199,10 +199,10 @@ MoveInstr::MoveInstr(Instruction *MovedI) : MovedI(MovedI) {
}
void MoveInstr::revert(Tracker &Tracker) {
- if (auto *NextI = NextInstrOrBB.dyn_cast<Instruction *>()) {
+ if (auto *NextI = dyn_cast<Instruction *>(NextInstrOrBB)) {
MovedI->moveBefore(NextI);
} else {
- auto *BB = NextInstrOrBB.get<BasicBlock *>();
+ auto *BB = cast<BasicBlock *>(NextInstrOrBB);
MovedI->moveBefore(*BB, BB->end());
}
}
diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp b/llvm/lib/Transforms/Scalar/SROA.cpp
index 4a23e2bee5ba25..d80af26451ac75 100644
--- a/llvm/lib/Transforms/Scalar/SROA.cpp
+++ b/llvm/lib/Transforms/Scalar/SROA.cpp
@@ -5166,11 +5166,9 @@ insertNewDbgInst(DIBuilder &DIB, DbgAssignIntrinsic *Orig, AllocaInst *NewAddr,
DIAssignID::getDistinct(NewAddr->getContext()));
}
- Instruction *NewAssign =
- DIB.insertDbgAssign(NewAddr, Orig->getValue(), Orig->getVariable(),
- NewFragmentExpr, NewAddr, NewAddrExpr,
- Orig->getDebugLoc())
- .get<Instruction *>();
+ Instruction *NewAssign = cast<Instruction *>(DIB.insertDbgAssign(
+ NewAddr, Orig->getValue(), Orig->getVariable(), NewFragmentExpr, NewAddr,
+ NewAddrExpr, Orig->getDebugLoc()));
LLVM_DEBUG(dbgs() << "Created new assign intrinsic: " << *NewAssign << "\n");
(void)NewAssign;
}
diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp
index 768765b6c1e632..509b6d62265517 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -1696,7 +1696,7 @@ static void insertDbgValueOrDbgVariableRecord(DIBuilder &Builder, Value *DV,
if (!UseNewDbgInfoFormat) {
auto DbgVal = Builder.insertDbgValueIntrinsic(DV, DIVar, DIExpr, NewLoc,
(Instruction *)nullptr);
- DbgVal.get<Instruction *>()->insertBefore(Instr);
+ cast<Instruction *>(DbgVal)->insertBefore(Instr);
} else {
// RemoveDIs: if we're using the new debug-info format, allocate a
// DbgVariableRecord directly instead of a dbg.value intrinsic.
@@ -1713,7 +1713,7 @@ static void insertDbgValueOrDbgVariableRecordAfter(
if (!UseNewDbgInfoFormat) {
auto DbgVal = Builder.insertDbgValueIntrinsic(DV, DIVar, DIExpr, NewLoc,
(Instruction *)nullptr);
- DbgVal.get<Instruction *>()->insertAfter(&*Instr);
+ cast<Instruction *>(DbgVal)->insertAfter(&*Instr);
} else {
// RemoveDIs: if we're using the new debug-info format, allocate a
// DbgVariableRecord directly instead of a dbg.value intrinsic.
>From a44ee8ec1c87be76e147d97f3be90a7e8630421b Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu at google.com>
Date: Sun, 10 Nov 2024 07:24:27 -0800
Subject: [PATCH 19/31] [TableGen] Use heterogenous lookups with std::map (NFC)
(#115633)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
---
clang/utils/TableGen/NeonEmitter.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/clang/utils/TableGen/NeonEmitter.cpp b/clang/utils/TableGen/NeonEmitter.cpp
index c6d82646b40de2..7081e5c9ae93e8 100644
--- a/clang/utils/TableGen/NeonEmitter.cpp
+++ b/clang/utils/TableGen/NeonEmitter.cpp
@@ -578,7 +578,7 @@ class Intrinsic {
class NeonEmitter {
const RecordKeeper &Records;
DenseMap<const Record *, ClassKind> ClassMap;
- std::map<std::string, std::deque<Intrinsic>> IntrinsicMap;
+ std::map<std::string, std::deque<Intrinsic>, std::less<>> IntrinsicMap;
unsigned UniqueNumber;
void createIntrinsic(const Record *R, SmallVectorImpl<Intrinsic *> &Out);
@@ -1937,9 +1937,9 @@ void Intrinsic::indexBody() {
Intrinsic &NeonEmitter::getIntrinsic(StringRef Name, ArrayRef<Type> Types,
std::optional<std::string> MangledName) {
// First, look up the name in the intrinsic map.
- assert_with_loc(IntrinsicMap.find(Name.str()) != IntrinsicMap.end(),
+ assert_with_loc(IntrinsicMap.find(Name) != IntrinsicMap.end(),
("Intrinsic '" + Name + "' not found!").str());
- auto &V = IntrinsicMap.find(Name.str())->second;
+ auto &V = IntrinsicMap.find(Name)->second;
std::vector<Intrinsic *> GoodVec;
// Create a string to print if we end up failing.
>From 2c0f463b2546a98e6215f3a85940ab9c0971d2aa Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu at google.com>
Date: Sun, 10 Nov 2024 07:24:47 -0800
Subject: [PATCH 20/31] [Vectorize] Simplify code with DenseMap::operator[]
(NFC) (#115635)
---
llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp b/llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
index dd005682203b75..f653269713b30b 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
@@ -297,12 +297,12 @@ void UnrollState::unrollRecipeByUF(VPRecipeBase &R) {
if (auto *Red = dyn_cast<VPReductionRecipe>(&R)) {
auto *Phi = cast<VPReductionPHIRecipe>(R.getOperand(0));
if (Phi->isOrdered()) {
- auto Ins = VPV2Parts.insert({Phi, {}});
+ auto &Parts = VPV2Parts[Phi];
if (Part == 1) {
- Ins.first->second.clear();
- Ins.first->second.push_back(Red);
+ Parts.clear();
+ Parts.push_back(Red);
}
- Ins.first->second.push_back(Copy->getVPSingleValue());
+ Parts.push_back(Copy->getVPSingleValue());
Phi->setOperand(1, Copy->getVPSingleValue());
}
}
>From 1e25c921d523151e6ed2ffe86029ea2e2b267a6c Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu at google.com>
Date: Sun, 10 Nov 2024 07:25:04 -0800
Subject: [PATCH 21/31] [AArch64/GISel] Remove unused includes (NFC) (#115636)
Identified with misc-include-cleaner.
---
llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp | 1 -
llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp | 2 --
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp | 1 -
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 2 --
.../lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp | 2 --
llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp | 3 ---
llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp | 1 -
llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp | 1 -
8 files changed, 13 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index 065858c4289447..15f1c99e87246b 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -47,7 +47,6 @@
#include <algorithm>
#include <cassert>
#include <cstdint>
-#include <iterator>
#define DEBUG_TYPE "aarch64-call-lowering"
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp b/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
index a2b909205ea84b..0b798509c26da5 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.cpp
@@ -9,11 +9,9 @@
/// GlobalISel pipeline.
//===----------------------------------------------------------------------===//
#include "AArch64GlobalISelUtils.h"
-#include "AArch64InstrInfo.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/InstrTypes.h"
-#include "llvm/Support/raw_ostream.h"
using namespace llvm;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index a08d379936abd6..5000078928a1d2 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -42,7 +42,6 @@
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicsAArch64.h"
-#include "llvm/IR/PatternMatch.h"
#include "llvm/IR/Type.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 3677cfdaba3b21..d42ecc1c72dce9 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -12,7 +12,6 @@
//===----------------------------------------------------------------------===//
#include "AArch64LegalizerInfo.h"
-#include "AArch64RegisterBankInfo.h"
#include "AArch64Subtarget.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
@@ -24,7 +23,6 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h"
-#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsAArch64.h"
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
index 0ba3a543d114ac..13dd934543a709 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
@@ -23,10 +23,8 @@
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Instructions.h"
-#include "llvm/Support/Debug.h"
#define GET_GICOMBINER_DEPS
#include "AArch64GenO0PreLegalizeGICombiner.inc"
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 41bd21779fe319..56d70ffdece713 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -23,10 +23,8 @@
#include "AArch64GlobalISelUtils.h"
#include "AArch64PerfectShuffle.h"
#include "AArch64Subtarget.h"
-#include "AArch64TargetMachine.h"
#include "GISel/AArch64LegalizerInfo.h"
#include "MCTargetDesc/AArch64MCTargetDesc.h"
-#include "TargetInfo/AArch64TargetInfo.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/CodeGen/GlobalISel/Combiner.h"
#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
@@ -46,7 +44,6 @@
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/InstrTypes.h"
#include "llvm/InitializePasses.h"
-#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include <optional>
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index 6e689d743804ac..80459827c30f3f 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -28,7 +28,6 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Instructions.h"
-#include "llvm/Support/Debug.h"
#define GET_GICOMBINER_DEPS
#include "AArch64GenPreLegalizeGICombiner.inc"
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index 8d63c36eb015f3..d9c558819db3d4 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -32,7 +32,6 @@
#include "llvm/IR/IntrinsicsAArch64.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Threading.h"
-#include <algorithm>
#include <cassert>
#define GET_TARGET_REGBANK_IMPL
>From 15ce2e183fb801ff418eb1347a9d5893e5665782 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu at google.com>
Date: Sun, 10 Nov 2024 07:50:24 -0800
Subject: [PATCH 22/31] [lldb] Use heterogenous lookups with std::map (NFC)
(#115590) (#115634)
Heterogenous lookups allow us to call find with StringRef, avoiding a
temporary heap allocation of std::string.
---
lldb/include/lldb/Interpreter/CommandObject.h | 10 ++++++----
lldb/source/Commands/CommandObjectMultiword.cpp | 4 ++--
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/lldb/include/lldb/Interpreter/CommandObject.h b/lldb/include/lldb/Interpreter/CommandObject.h
index c5167e5e0ecb6a..e6fea9e022c43a 100644
--- a/lldb/include/lldb/Interpreter/CommandObject.h
+++ b/lldb/include/lldb/Interpreter/CommandObject.h
@@ -35,8 +35,9 @@ namespace lldb_private {
template <typename ValueType>
int AddNamesMatchingPartialString(
- const std::map<std::string, ValueType> &in_map, llvm::StringRef cmd_str,
- StringList &matches, StringList *descriptions = nullptr) {
+ const std::map<std::string, ValueType, std::less<>> &in_map,
+ llvm::StringRef cmd_str, StringList &matches,
+ StringList *descriptions = nullptr) {
int number_added = 0;
const bool add_all = cmd_str.empty();
@@ -54,7 +55,8 @@ int AddNamesMatchingPartialString(
}
template <typename ValueType>
-size_t FindLongestCommandWord(std::map<std::string, ValueType> &dict) {
+size_t
+FindLongestCommandWord(std::map<std::string, ValueType, std::less<>> &dict) {
auto end = dict.end();
size_t max_len = 0;
@@ -107,7 +109,7 @@ class CommandObject : public std::enable_shared_from_this<CommandObject> {
typedef std::vector<CommandArgumentData>
CommandArgumentEntry; // Used to build individual command argument lists
- typedef std::map<std::string, lldb::CommandObjectSP> CommandMap;
+ typedef std::map<std::string, lldb::CommandObjectSP, std::less<>> CommandMap;
CommandObject(CommandInterpreter &interpreter, llvm::StringRef name,
llvm::StringRef help = "", llvm::StringRef syntax = "",
diff --git a/lldb/source/Commands/CommandObjectMultiword.cpp b/lldb/source/Commands/CommandObjectMultiword.cpp
index b4cdfea9b1a3ef..c99b75ff29144d 100644
--- a/lldb/source/Commands/CommandObjectMultiword.cpp
+++ b/lldb/source/Commands/CommandObjectMultiword.cpp
@@ -32,7 +32,7 @@ CommandObjectMultiword::GetSubcommandSPExact(llvm::StringRef sub_cmd) {
if (m_subcommand_dict.empty())
return {};
- auto pos = m_subcommand_dict.find(std::string(sub_cmd));
+ auto pos = m_subcommand_dict.find(sub_cmd);
if (pos == m_subcommand_dict.end())
return {};
@@ -64,7 +64,7 @@ CommandObjectSP CommandObjectMultiword::GetSubcommandSP(llvm::StringRef sub_cmd,
// function, since I now know I have an exact match...
sub_cmd = matches->GetStringAtIndex(0);
- pos = m_subcommand_dict.find(std::string(sub_cmd));
+ pos = m_subcommand_dict.find(sub_cmd);
if (pos != m_subcommand_dict.end())
return_cmd_sp = pos->second;
}
>From ff0698b258eba9afd888159358c7369c3f85e9ae Mon Sep 17 00:00:00 2001
From: Will <william.fedele1 at gmail.com>
Date: Sun, 10 Nov 2024 10:51:29 -0500
Subject: [PATCH 23/31] [LangRef] Fix examples for float to int saturating
intrinsics (#115629)
As per the [LangRef:Simple
Constants](https://llvm.org/docs/LangRef.html#simple-constants), exact
decimal values of floating-point constants are required. For instance,
23.9 is a repeating decimal in binary and results in the reported error.
https://godbolt.org/z/1h7ETPnf6
Fixes #113529.
---
llvm/docs/LangRef.rst | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index e426140f328315..8fe4b1bd40e215 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -20392,8 +20392,8 @@ Example:
.. code-block:: text
- %a = call i8 @llvm.fptoui.sat.i8.f32(float 123.9) ; yields i8: 123
- %b = call i8 @llvm.fptoui.sat.i8.f32(float -5.7) ; yields i8: 0
+ %a = call i8 @llvm.fptoui.sat.i8.f32(float 123.875) ; yields i8: 123
+ %b = call i8 @llvm.fptoui.sat.i8.f32(float -5.75) ; yields i8: 0
%c = call i8 @llvm.fptoui.sat.i8.f32(float 377.0) ; yields i8: 255
%d = call i8 @llvm.fptoui.sat.i8.f32(float 0xFFF8000000000000) ; yields i8: 0
@@ -20445,8 +20445,8 @@ Example:
.. code-block:: text
- %a = call i8 @llvm.fptosi.sat.i8.f32(float 23.9) ; yields i8: 23
- %b = call i8 @llvm.fptosi.sat.i8.f32(float -130.8) ; yields i8: -128
+ %a = call i8 @llvm.fptosi.sat.i8.f32(float 23.875) ; yields i8: 23
+ %b = call i8 @llvm.fptosi.sat.i8.f32(float -130.75) ; yields i8: -128
%c = call i8 @llvm.fptosi.sat.i8.f32(float 999.0) ; yields i8: 127
%d = call i8 @llvm.fptosi.sat.i8.f32(float 0xFFF8000000000000) ; yields i8: 0
>From 028ea71fdda0c02cd11421cd1d26bec6f378666e Mon Sep 17 00:00:00 2001
From: Julian Schmidt <git.julian.schmidt at gmail.com>
Date: Sun, 10 Nov 2024 18:26:42 +0100
Subject: [PATCH 24/31] [clang-tidy] fix insertion location for function
pointers in cppcoreguidelines-init-variables (#112091)
Previously, the insertion location for the `= nullptr` fix would be
after the variable name. However, if the variable is of type function
pointer that is not an alias, then the insertion would happen inside the
type specification: `void (*a1)(void*);` -> `void (*a1 =
nullptr)(void*);`.
With this change, the insertion location will be at the next
'terminator'. That is, at the next `,` or `;`, as that will finish the
current declaration: `void (a1)(void*) = nullptr;`.
Fixes #112089
---
.../cppcoreguidelines/InitVariablesCheck.cpp | 8 +++++---
clang-tools-extra/docs/ReleaseNotes.rst | 10 +++++++---
.../checkers/cppcoreguidelines/init-variables.cpp | 14 ++++++++++++++
3 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/clang-tools-extra/clang-tidy/cppcoreguidelines/InitVariablesCheck.cpp b/clang-tools-extra/clang-tidy/cppcoreguidelines/InitVariablesCheck.cpp
index bdba2314c7056f..3eef2fd12cc8e5 100644
--- a/clang-tools-extra/clang-tidy/cppcoreguidelines/InitVariablesCheck.cpp
+++ b/clang-tools-extra/clang-tidy/cppcoreguidelines/InitVariablesCheck.cpp
@@ -8,9 +8,10 @@
#include "InitVariablesCheck.h"
+#include "../utils/LexerUtils.h"
#include "clang/AST/ASTContext.h"
+#include "clang/AST/Type.h"
#include "clang/ASTMatchers/ASTMatchFinder.h"
-#include "clang/Lex/PPCallbacks.h"
#include "clang/Lex/Preprocessor.h"
#include <optional>
@@ -107,8 +108,9 @@ void InitVariablesCheck::check(const MatchFinder::MatchResult &Result) {
<< MatchedDecl;
if (*InitializationString != nullptr)
Diagnostic << FixItHint::CreateInsertion(
- MatchedDecl->getLocation().getLocWithOffset(
- MatchedDecl->getName().size()),
+ utils::lexer::findNextTerminator(MatchedDecl->getLocation(),
+ *Result.SourceManager,
+ Result.Context->getLangOpts()),
*InitializationString);
if (AddMathInclude) {
Diagnostic << IncludeInserter.createIncludeInsertion(
diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst
index c79f423bac5f06..442fb7180555ea 100644
--- a/clang-tools-extra/docs/ReleaseNotes.rst
+++ b/clang-tools-extra/docs/ReleaseNotes.rst
@@ -194,6 +194,10 @@ Changes in existing checks
fix false positive that floating point variable is only used in increment
expression.
+- Improved :doc:`cppcoreguidelines-init-variables
+ <clang-tidy/checks/cppcoreguidelines/init-variables>` check by fixing the
+ insertion location for function pointers.
+
- Improved :doc:`cppcoreguidelines-prefer-member-initializer
<clang-tidy/checks/cppcoreguidelines/prefer-member-initializer>` check to
avoid false positive when member initialization depends on a structured
@@ -212,9 +216,9 @@ Changes in existing checks
false positive for C++23 deducing this.
- Improved :doc:`modernize-avoid-c-arrays
- <clang-tidy/checks/modernize/avoid-c-arrays>` check to suggest using ``std::span``
- as a replacement for parameters of incomplete C array type in C++20 and
- ``std::array`` or ``std::vector`` before C++20.
+ <clang-tidy/checks/modernize/avoid-c-arrays>` check to suggest using
+ ``std::span`` as a replacement for parameters of incomplete C array type in
+ C++20 and ``std::array`` or ``std::vector`` before C++20.
- Improved :doc:`modernize-loop-convert
<clang-tidy/checks/modernize/loop-convert>` check to fix false positive when
diff --git a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/init-variables.cpp b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/init-variables.cpp
index e3d50946d1cb8f..824431c1bf52fd 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/init-variables.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/init-variables.cpp
@@ -134,3 +134,17 @@ void test_clang_diagnostic_error() {
// CHECK-MESSAGES: :[[@LINE-1]]:3: error: unknown type name 'UnknownType' [clang-diagnostic-error]
// CHECK-FIXES-NOT: {{^}} UnknownType b = 0;{{$}}
}
+
+namespace gh112089 {
+ void foo(void*);
+ using FPtr = void(*)(void*);
+ void test() {
+ void(*a1)(void*);
+ // CHECK-MESSAGES: :[[@LINE-1]]:15: warning: variable 'a1' is not initialized [cppcoreguidelines-init-variables]
+ // CHECK-FIXES: void(*a1)(void*) = nullptr;
+ FPtr a2;
+ // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: variable 'a2' is not initialized [cppcoreguidelines-init-variables]
+ // CHECK-FIXES: FPtr a2 = nullptr;
+ }
+} // namespace gh112089
+
>From 7111d031f19ce7d523796b4812d6afcb2958b025 Mon Sep 17 00:00:00 2001
From: Fangrui Song <i at maskray.me>
Date: Sun, 10 Nov 2024 09:54:22 -0800
Subject: [PATCH 25/31] [Xtensa] Fix Clang -Wundefined-bool-conversion after
#113450
---
llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 2 --
1 file changed, 2 deletions(-)
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
index 4c440da715fefe..7e00215ef3b971 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
@@ -529,8 +529,6 @@ void XtensaInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
unsigned XtensaInstrInfo::insertConstBranchAtInst(
MachineBasicBlock &MBB, MachineInstr *I, int64_t offset,
ArrayRef<MachineOperand> Cond, DebugLoc DL, int *BytesAdded) const {
- // Shouldn't be a fall through.
- assert(&MBB && "InsertBranch must not be told to insert a fallthrough");
assert(Cond.size() <= 4 &&
"Xtensa branch conditions have less than four components!");
>From 3006dddfe091bcb95924d72dddbb84f73186a344 Mon Sep 17 00:00:00 2001
From: Janis Heims <janis.heims at undertheprinter.com>
Date: Sun, 10 Nov 2024 23:43:25 +0000
Subject: [PATCH 26/31] [M68k] fix call frame destruction elimination when
returning structs (#107579)
Fixes #106213.
This adjusts `eliminateCallFramePseudoInstr` to match the behaviour of
the X86 backend.
---
llvm/lib/Target/M68k/M68kFrameLowering.cpp | 6 +-
llvm/test/CodeGen/M68k/multiple-return.ll | 74 +++++++++++++++++++++-
2 files changed, 76 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/M68k/M68kFrameLowering.cpp b/llvm/lib/Target/M68k/M68kFrameLowering.cpp
index 4245061f0ae749..721395027b512e 100644
--- a/llvm/lib/Target/M68k/M68kFrameLowering.cpp
+++ b/llvm/lib/Target/M68k/M68kFrameLowering.cpp
@@ -33,6 +33,8 @@
using namespace llvm;
+#define DEBUG_TYPE "m68k-frame"
+
M68kFrameLowering::M68kFrameLowering(const M68kSubtarget &STI, Align Alignment)
: TargetFrameLowering(StackGrowsDown, Alignment, -4), STI(STI),
TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
@@ -231,8 +233,8 @@ MachineBasicBlock::iterator M68kFrameLowering::eliminateCallFramePseudoInstr(
unsigned Opcode = I->getOpcode();
bool IsDestroy = Opcode == TII.getCallFrameDestroyOpcode();
DebugLoc DL = I->getDebugLoc();
- uint64_t Amount = !ReserveCallFrame ? I->getOperand(0).getImm() : 0;
- uint64_t InternalAmt = (IsDestroy && Amount) ? I->getOperand(1).getImm() : 0;
+ uint64_t Amount = I->getOperand(0).getImm();
+ uint64_t InternalAmt = (IsDestroy || Amount) ? I->getOperand(1).getImm() : 0;
I = MBB.erase(I);
if (!ReserveCallFrame) {
diff --git a/llvm/test/CodeGen/M68k/multiple-return.ll b/llvm/test/CodeGen/M68k/multiple-return.ll
index f52f422b194f59..8e97908324f057 100644
--- a/llvm/test/CodeGen/M68k/multiple-return.ll
+++ b/llvm/test/CodeGen/M68k/multiple-return.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s
-define { i32, i32, i32, i32 } @test() {
-; CHECK-LABEL: test:
+define { i32, i32, i32, i32 } @test0() {
+; CHECK-LABEL: test0:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0: ; %start
; CHECK-NEXT: move.l (4,%sp), %a0
@@ -18,3 +18,73 @@ define { i32, i32, i32, i32 } @test() {
start:
ret { i32, i32, i32, i32 } { i32 13, i32 17, i32 19, i32 23 }
}
+
+define void @call_test0() {
+; CHECK-LABEL: call_test0:
+; CHECK: .cfi_startproc
+; CHECK-NEXT: ; %bb.0: ; %start
+; CHECK-NEXT: suba.l #20, %sp
+; CHECK-NEXT: .cfi_def_cfa_offset -24
+; CHECK-NEXT: lea (4,%sp), %a0
+; CHECK-NEXT: move.l %a0, (%sp)
+; CHECK-NEXT: jsr test0
+; CHECK-NEXT: adda.l #16, %sp
+; CHECK-NEXT: rts
+start:
+ %val = call { i32, i32, i32, i32 } @test0()
+ ret void
+}
+
+define void @test1(ptr sret({ i32, i32, i32, i32 }) %ret_val) {
+; CHECK-LABEL: test1:
+; CHECK: .cfi_startproc
+; CHECK-NEXT: ; %bb.0: ; %start
+; CHECK-NEXT: move.l (4,%sp), %d0
+; CHECK-NEXT: move.l (%sp), %a1
+; CHECK-NEXT: adda.l #4, %sp
+; CHECK-NEXT: move.l %a1, (%sp)
+; CHECK-NEXT: rts
+start:
+ ret void
+}
+
+define void @call_test1() {
+; CHECK-LABEL: call_test1:
+; CHECK: .cfi_startproc
+; CHECK-NEXT: ; %bb.0: ; %start
+; CHECK-NEXT: suba.l #20, %sp
+; CHECK-NEXT: .cfi_def_cfa_offset -24
+; CHECK-NEXT: lea (4,%sp), %a0
+; CHECK-NEXT: move.l %a0, (%sp)
+; CHECK-NEXT: jsr test1
+; CHECK-NEXT: adda.l #16, %sp
+; CHECK-NEXT: rts
+start:
+ %ret_val = alloca { i32, i32, i32, i32 }
+ call void @test1(ptr %ret_val)
+ ret void
+}
+
+define i32 @test2() {
+; CHECK-LABEL: test2:
+; CHECK: .cfi_startproc
+; CHECK-NEXT: ; %bb.0: ; %start
+; CHECK-NEXT: moveq #13, %d0
+; CHECK-NEXT: rts
+start:
+ ret i32 13
+}
+
+define void @call_test2() {
+; CHECK-LABEL: call_test2:
+; CHECK: .cfi_startproc
+; CHECK-NEXT: ; %bb.0: ; %start
+; CHECK-NEXT: suba.l #4, %sp
+; CHECK-NEXT: .cfi_def_cfa_offset -8
+; CHECK-NEXT: jsr test2
+; CHECK-NEXT: adda.l #4, %sp
+; CHECK-NEXT: rts
+start:
+ %0 = call i32 @test2()
+ ret void
+}
>From dc11c0601577afb8f67513d041ee25dabe3555b9 Mon Sep 17 00:00:00 2001
From: Lang Hames <lhames at gmail.com>
Date: Mon, 11 Nov 2024 11:34:56 +1100
Subject: [PATCH 27/31] [ORC] Move absoluteSymbols from Core.h to new
AbsoluteSymbols.h header. NFC.
Continuing Core.h clean-up.
If you see any errors about a missing absoluteSymbols function you need to
include the new AbsoluteSymbols.h header.
---
.../LLJITWithInitializers.cpp | 1 +
.../ExecutionEngine/Orc/AbsoluteSymbols.h | 59 +++++++++++++++++++
llvm/include/llvm/ExecutionEngine/Orc/Core.h | 34 -----------
llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h | 1 +
.../ExecutionEngine/Orc/AbsoluteSymbols.cpp | 57 ++++++++++++++++++
llvm/lib/ExecutionEngine/Orc/CMakeLists.txt | 1 +
llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp | 1 +
llvm/lib/ExecutionEngine/Orc/Core.cpp | 41 -------------
.../ExecutionEngine/Orc/ELFNixPlatform.cpp | 1 +
.../Orc/EPCDynamicLibrarySearchGenerator.cpp | 2 +
.../ExecutionEngine/Orc/ExecutionUtils.cpp | 1 +
.../lib/ExecutionEngine/Orc/MachOPlatform.cpp | 1 +
.../ExecutionEngine/Orc/OrcV2CBindings.cpp | 1 +
llvm/lib/ExecutionEngine/Orc/Speculation.cpp | 2 +
llvm/tools/lli/lli.cpp | 1 +
llvm/tools/llvm-jitlink/llvm-jitlink.cpp | 1 +
.../ExecutionEngine/Orc/CoreAPIsTest.cpp | 1 +
...ecutionSessionWrapperFunctionCallsTest.cpp | 1 +
.../Orc/LookupAndRecordAddrsTest.cpp | 4 +-
.../Orc/ReOptimizeLayerTest.cpp | 1 +
20 files changed, 135 insertions(+), 77 deletions(-)
create mode 100644 llvm/include/llvm/ExecutionEngine/Orc/AbsoluteSymbols.h
create mode 100644 llvm/lib/ExecutionEngine/Orc/AbsoluteSymbols.cpp
diff --git a/llvm/examples/OrcV2Examples/LLJITWithInitializers/LLJITWithInitializers.cpp b/llvm/examples/OrcV2Examples/LLJITWithInitializers/LLJITWithInitializers.cpp
index 32b51c31485962..704fd9c1483307 100644
--- a/llvm/examples/OrcV2Examples/LLJITWithInitializers/LLJITWithInitializers.cpp
+++ b/llvm/examples/OrcV2Examples/LLJITWithInitializers/LLJITWithInitializers.cpp
@@ -19,6 +19,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/ADT/StringMap.h"
+#include "llvm/ExecutionEngine/Orc/AbsoluteSymbols.h"
#include "llvm/ExecutionEngine/Orc/LLJIT.h"
#include "llvm/Support/InitLLVM.h"
#include "llvm/Support/TargetSelect.h"
diff --git a/llvm/include/llvm/ExecutionEngine/Orc/AbsoluteSymbols.h b/llvm/include/llvm/ExecutionEngine/Orc/AbsoluteSymbols.h
new file mode 100644
index 00000000000000..d58fc8b11f5046
--- /dev/null
+++ b/llvm/include/llvm/ExecutionEngine/Orc/AbsoluteSymbols.h
@@ -0,0 +1,59 @@
+//===------ AbsoluteSymbols.h - Absolute symbols utilities ------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// absoluteSymbols function and related utilities.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_EXECUTIONENGINE_ORC_ABSOLUTESYMBOLS_H
+#define LLVM_EXECUTIONENGINE_ORC_ABSOLUTESYMBOLS_H
+
+#include "llvm/ExecutionEngine/Orc/MaterializationUnit.h"
+
+namespace llvm::orc {
+
+/// A MaterializationUnit implementation for pre-existing absolute symbols.
+///
+/// All symbols will be resolved and marked ready as soon as the unit is
+/// materialized.
+class AbsoluteSymbolsMaterializationUnit : public MaterializationUnit {
+public:
+ AbsoluteSymbolsMaterializationUnit(SymbolMap Symbols);
+
+ StringRef getName() const override;
+
+private:
+ void materialize(std::unique_ptr<MaterializationResponsibility> R) override;
+ void discard(const JITDylib &JD, const SymbolStringPtr &Name) override;
+ static MaterializationUnit::Interface extractFlags(const SymbolMap &Symbols);
+
+ SymbolMap Symbols;
+};
+
+/// Create an AbsoluteSymbolsMaterializationUnit with the given symbols.
+/// Useful for inserting absolute symbols into a JITDylib. E.g.:
+/// \code{.cpp}
+/// JITDylib &JD = ...;
+/// SymbolStringPtr Foo = ...;
+/// ExecutorSymbolDef FooSym = ...;
+/// if (auto Err = JD.define(absoluteSymbols({
+/// { Foo, FooSym },
+/// { Bar, BarSym }
+/// })))
+/// return Err;
+/// \endcode
+///
+inline std::unique_ptr<AbsoluteSymbolsMaterializationUnit>
+absoluteSymbols(SymbolMap Symbols) {
+ return std::make_unique<AbsoluteSymbolsMaterializationUnit>(
+ std::move(Symbols));
+}
+
+} // namespace llvm::orc
+
+#endif // LLVM_EXECUTIONENGINE_ORC_ABSOLUTESYMBOLS_H
diff --git a/llvm/include/llvm/ExecutionEngine/Orc/Core.h b/llvm/include/llvm/ExecutionEngine/Orc/Core.h
index 119d3d878206fb..e892005c53d8ec 100644
--- a/llvm/include/llvm/ExecutionEngine/Orc/Core.h
+++ b/llvm/include/llvm/ExecutionEngine/Orc/Core.h
@@ -666,40 +666,6 @@ class MaterializationResponsibility {
SymbolStringPtr InitSymbol;
};
-/// A MaterializationUnit implementation for pre-existing absolute symbols.
-///
-/// All symbols will be resolved and marked ready as soon as the unit is
-/// materialized.
-class AbsoluteSymbolsMaterializationUnit : public MaterializationUnit {
-public:
- AbsoluteSymbolsMaterializationUnit(SymbolMap Symbols);
-
- StringRef getName() const override;
-
-private:
- void materialize(std::unique_ptr<MaterializationResponsibility> R) override;
- void discard(const JITDylib &JD, const SymbolStringPtr &Name) override;
- static MaterializationUnit::Interface extractFlags(const SymbolMap &Symbols);
-
- SymbolMap Symbols;
-};
-
-/// Create an AbsoluteSymbolsMaterializationUnit with the given symbols.
-/// Useful for inserting absolute symbols into a JITDylib. E.g.:
-/// \code{.cpp}
-/// JITDylib &JD = ...;
-/// SymbolStringPtr Foo = ...;
-/// ExecutorSymbolDef FooSym = ...;
-/// if (auto Err = JD.define(absoluteSymbols({{Foo, FooSym}})))
-/// return Err;
-/// \endcode
-///
-inline std::unique_ptr<AbsoluteSymbolsMaterializationUnit>
-absoluteSymbols(SymbolMap Symbols) {
- return std::make_unique<AbsoluteSymbolsMaterializationUnit>(
- std::move(Symbols));
-}
-
/// A materialization unit for symbol aliases. Allows existing symbols to be
/// aliased with alternate flags.
class ReExportsMaterializationUnit : public MaterializationUnit {
diff --git a/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h b/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
index a2364b4515f01b..ebff2106e9d72b 100644
--- a/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
+++ b/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
@@ -14,6 +14,7 @@
#define LLVM_EXECUTIONENGINE_ORC_LLJIT_H
#include "llvm/ADT/SmallSet.h"
+#include "llvm/ExecutionEngine/Orc/AbsoluteSymbols.h"
#include "llvm/ExecutionEngine/Orc/CompileOnDemandLayer.h"
#include "llvm/ExecutionEngine/Orc/CompileUtils.h"
#include "llvm/ExecutionEngine/Orc/ExecutionUtils.h"
diff --git a/llvm/lib/ExecutionEngine/Orc/AbsoluteSymbols.cpp b/llvm/lib/ExecutionEngine/Orc/AbsoluteSymbols.cpp
new file mode 100644
index 00000000000000..d37dad8925e9a6
--- /dev/null
+++ b/llvm/lib/ExecutionEngine/Orc/AbsoluteSymbols.cpp
@@ -0,0 +1,57 @@
+//===---------- AbsoluteSymbols.cpp - Absolute symbols utilities ----------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ExecutionEngine/Orc/AbsoluteSymbols.h"
+#include "llvm/ExecutionEngine/Orc/Core.h"
+
+#define DEBUG_TYPE "orc"
+
+namespace llvm::orc {
+
+AbsoluteSymbolsMaterializationUnit::AbsoluteSymbolsMaterializationUnit(
+ SymbolMap Symbols)
+ : MaterializationUnit(extractFlags(Symbols)), Symbols(std::move(Symbols)) {}
+
+StringRef AbsoluteSymbolsMaterializationUnit::getName() const {
+ return "<Absolute Symbols>";
+}
+
+void AbsoluteSymbolsMaterializationUnit::materialize(
+ std::unique_ptr<MaterializationResponsibility> R) {
+ // Even though these are just absolute symbols we need to check for failure
+ // to resolve/emit: the tracker for these symbols may have been removed while
+ // the materialization was in flight (e.g. due to a failure in some action
+ // triggered by the queries attached to the resolution/emission of these
+ // symbols).
+ if (auto Err = R->notifyResolved(Symbols)) {
+ R->getExecutionSession().reportError(std::move(Err));
+ R->failMaterialization();
+ return;
+ }
+ if (auto Err = R->notifyEmitted({})) {
+ R->getExecutionSession().reportError(std::move(Err));
+ R->failMaterialization();
+ return;
+ }
+}
+
+void AbsoluteSymbolsMaterializationUnit::discard(const JITDylib &JD,
+ const SymbolStringPtr &Name) {
+ assert(Symbols.count(Name) && "Symbol is not part of this MU");
+ Symbols.erase(Name);
+}
+
+MaterializationUnit::Interface
+AbsoluteSymbolsMaterializationUnit::extractFlags(const SymbolMap &Symbols) {
+ SymbolFlagsMap Flags;
+ for (const auto &[Name, Def] : Symbols)
+ Flags[Name] = Def.getFlags();
+ return MaterializationUnit::Interface(std::move(Flags), nullptr);
+}
+
+} // namespace llvm::orc
diff --git a/llvm/lib/ExecutionEngine/Orc/CMakeLists.txt b/llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
index 008875118fdeff..7a73ab56a5d97c 100644
--- a/llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
+++ b/llvm/lib/ExecutionEngine/Orc/CMakeLists.txt
@@ -7,6 +7,7 @@ if( CMAKE_HOST_UNIX AND HAVE_LIBRT )
endif()
add_llvm_component_library(LLVMOrcJIT
+ AbsoluteSymbols.cpp
COFFVCRuntimeSupport.cpp
COFFPlatform.cpp
CompileOnDemandLayer.cpp
diff --git a/llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp b/llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
index f46cb906bb7556..2176acc5bba807 100644
--- a/llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
@@ -7,6 +7,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/ExecutionEngine/Orc/COFFPlatform.h"
+#include "llvm/ExecutionEngine/Orc/AbsoluteSymbols.h"
#include "llvm/ExecutionEngine/Orc/DebugUtils.h"
#include "llvm/ExecutionEngine/Orc/LookupAndRecordAddrs.h"
#include "llvm/ExecutionEngine/Orc/ObjectFileInterface.h"
diff --git a/llvm/lib/ExecutionEngine/Orc/Core.cpp b/llvm/lib/ExecutionEngine/Orc/Core.cpp
index 226216f781fe9e..78041993648834 100644
--- a/llvm/lib/ExecutionEngine/Orc/Core.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/Core.cpp
@@ -276,47 +276,6 @@ void AsynchronousSymbolQuery::detach() {
QueryRegistrations.clear();
}
-AbsoluteSymbolsMaterializationUnit::AbsoluteSymbolsMaterializationUnit(
- SymbolMap Symbols)
- : MaterializationUnit(extractFlags(Symbols)), Symbols(std::move(Symbols)) {}
-
-StringRef AbsoluteSymbolsMaterializationUnit::getName() const {
- return "<Absolute Symbols>";
-}
-
-void AbsoluteSymbolsMaterializationUnit::materialize(
- std::unique_ptr<MaterializationResponsibility> R) {
- // Even though these are just absolute symbols we need to check for failure
- // to resolve/emit: the tracker for these symbols may have been removed while
- // the materialization was in flight (e.g. due to a failure in some action
- // triggered by the queries attached to the resolution/emission of these
- // symbols).
- if (auto Err = R->notifyResolved(Symbols)) {
- R->getExecutionSession().reportError(std::move(Err));
- R->failMaterialization();
- return;
- }
- if (auto Err = R->notifyEmitted({})) {
- R->getExecutionSession().reportError(std::move(Err));
- R->failMaterialization();
- return;
- }
-}
-
-void AbsoluteSymbolsMaterializationUnit::discard(const JITDylib &JD,
- const SymbolStringPtr &Name) {
- assert(Symbols.count(Name) && "Symbol is not part of this MU");
- Symbols.erase(Name);
-}
-
-MaterializationUnit::Interface
-AbsoluteSymbolsMaterializationUnit::extractFlags(const SymbolMap &Symbols) {
- SymbolFlagsMap Flags;
- for (const auto &[Name, Def] : Symbols)
- Flags[Name] = Def.getFlags();
- return MaterializationUnit::Interface(std::move(Flags), nullptr);
-}
-
ReExportsMaterializationUnit::ReExportsMaterializationUnit(
JITDylib *SourceJD, JITDylibLookupFlags SourceJDLookupFlags,
SymbolAliasMap Aliases)
diff --git a/llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp b/llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
index 6cea9845a3403b..3874f25751b1a2 100644
--- a/llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp
@@ -14,6 +14,7 @@
#include "llvm/ExecutionEngine/JITLink/aarch64.h"
#include "llvm/ExecutionEngine/JITLink/ppc64.h"
#include "llvm/ExecutionEngine/JITLink/x86_64.h"
+#include "llvm/ExecutionEngine/Orc/AbsoluteSymbols.h"
#include "llvm/ExecutionEngine/Orc/DebugUtils.h"
#include "llvm/ExecutionEngine/Orc/ExecutionUtils.h"
#include "llvm/ExecutionEngine/Orc/LookupAndRecordAddrs.h"
diff --git a/llvm/lib/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.cpp b/llvm/lib/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.cpp
index 8490eee22aea56..2a93fcbf6c8c83 100644
--- a/llvm/lib/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.cpp
@@ -7,6 +7,8 @@
//===----------------------------------------------------------------------===//
#include "llvm/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.h"
+
+#include "llvm/ExecutionEngine/Orc/AbsoluteSymbols.h"
#include "llvm/ExecutionEngine/Orc/DebugUtils.h"
#include "llvm/Support/Error.h"
diff --git a/llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp b/llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
index 1dcf91443d55db..efaed1b82d0eb2 100644
--- a/llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/ExecutionUtils.cpp
@@ -8,6 +8,7 @@
#include "llvm/ExecutionEngine/Orc/ExecutionUtils.h"
#include "llvm/ExecutionEngine/JITLink/x86_64.h"
+#include "llvm/ExecutionEngine/Orc/AbsoluteSymbols.h"
#include "llvm/ExecutionEngine/Orc/Layer.h"
#include "llvm/ExecutionEngine/Orc/LoadLinkableFile.h"
#include "llvm/ExecutionEngine/Orc/MachO.h"
diff --git a/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp b/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
index e5609053c74d7b..822316c4bf996e 100644
--- a/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
@@ -12,6 +12,7 @@
#include "llvm/ExecutionEngine/JITLink/MachO.h"
#include "llvm/ExecutionEngine/JITLink/aarch64.h"
#include "llvm/ExecutionEngine/JITLink/x86_64.h"
+#include "llvm/ExecutionEngine/Orc/AbsoluteSymbols.h"
#include "llvm/ExecutionEngine/Orc/DebugUtils.h"
#include "llvm/ExecutionEngine/Orc/ExecutionUtils.h"
#include "llvm/ExecutionEngine/Orc/LookupAndRecordAddrs.h"
diff --git a/llvm/lib/ExecutionEngine/Orc/OrcV2CBindings.cpp b/llvm/lib/ExecutionEngine/Orc/OrcV2CBindings.cpp
index 453b8f86868adb..ae76cb08765e46 100644
--- a/llvm/lib/ExecutionEngine/Orc/OrcV2CBindings.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/OrcV2CBindings.cpp
@@ -11,6 +11,7 @@
#include "llvm-c/OrcEE.h"
#include "llvm-c/TargetMachine.h"
+#include "llvm/ExecutionEngine/Orc/AbsoluteSymbols.h"
#include "llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h"
#include "llvm/ExecutionEngine/Orc/LLJIT.h"
#include "llvm/ExecutionEngine/Orc/ObjectTransformLayer.h"
diff --git a/llvm/lib/ExecutionEngine/Orc/Speculation.cpp b/llvm/lib/ExecutionEngine/Orc/Speculation.cpp
index 70b536d2feda0f..74b9eb29bdccf3 100644
--- a/llvm/lib/ExecutionEngine/Orc/Speculation.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/Speculation.cpp
@@ -7,6 +7,8 @@
//===----------------------------------------------------------------------===//
#include "llvm/ExecutionEngine/Orc/Speculation.h"
+
+#include "llvm/ExecutionEngine/Orc/AbsoluteSymbols.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/IRBuilder.h"
diff --git a/llvm/tools/lli/lli.cpp b/llvm/tools/lli/lli.cpp
index 540c43889da758..dd275b73a0c7ec 100644
--- a/llvm/tools/lli/lli.cpp
+++ b/llvm/tools/lli/lli.cpp
@@ -24,6 +24,7 @@
#include "llvm/ExecutionEngine/JITSymbol.h"
#include "llvm/ExecutionEngine/MCJIT.h"
#include "llvm/ExecutionEngine/ObjectCache.h"
+#include "llvm/ExecutionEngine/Orc/AbsoluteSymbols.h"
#include "llvm/ExecutionEngine/Orc/DebugUtils.h"
#include "llvm/ExecutionEngine/Orc/Debugging/DebuggerSupport.h"
#include "llvm/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.h"
diff --git a/llvm/tools/llvm-jitlink/llvm-jitlink.cpp b/llvm/tools/llvm-jitlink/llvm-jitlink.cpp
index 261daae5e67f94..f6b631834b1e34 100644
--- a/llvm/tools/llvm-jitlink/llvm-jitlink.cpp
+++ b/llvm/tools/llvm-jitlink/llvm-jitlink.cpp
@@ -15,6 +15,7 @@
#include "llvm-jitlink.h"
#include "llvm/BinaryFormat/Magic.h"
#include "llvm/Config/llvm-config.h" // for LLVM_ON_UNIX, LLVM_ENABLE_THREADS
+#include "llvm/ExecutionEngine/Orc/AbsoluteSymbols.h"
#include "llvm/ExecutionEngine/Orc/COFFPlatform.h"
#include "llvm/ExecutionEngine/Orc/COFFVCRuntimeSupport.h"
#include "llvm/ExecutionEngine/Orc/DebugObjectManagerPlugin.h"
diff --git a/llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp b/llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
index 39a49eb1799936..a907dfcf2cec5b 100644
--- a/llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
+++ b/llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
@@ -9,6 +9,7 @@
#include "OrcTestCommon.h"
#include "llvm/ADT/ScopeExit.h"
#include "llvm/Config/llvm-config.h"
+#include "llvm/ExecutionEngine/Orc/AbsoluteSymbols.h"
#include "llvm/ExecutionEngine/Orc/Core.h"
#include "llvm/ExecutionEngine/Orc/Shared/OrcError.h"
#include "llvm/Testing/Support/Error.h"
diff --git a/llvm/unittests/ExecutionEngine/Orc/ExecutionSessionWrapperFunctionCallsTest.cpp b/llvm/unittests/ExecutionEngine/Orc/ExecutionSessionWrapperFunctionCallsTest.cpp
index 1b79e12ee168c8..a25da8a727de54 100644
--- a/llvm/unittests/ExecutionEngine/Orc/ExecutionSessionWrapperFunctionCallsTest.cpp
+++ b/llvm/unittests/ExecutionEngine/Orc/ExecutionSessionWrapperFunctionCallsTest.cpp
@@ -6,6 +6,7 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/ExecutionEngine/Orc/AbsoluteSymbols.h"
#include "llvm/ExecutionEngine/Orc/Core.h"
#include "llvm/ExecutionEngine/Orc/ExecutorProcessControl.h"
#include "llvm/Support/MSVCErrorWorkarounds.h"
diff --git a/llvm/unittests/ExecutionEngine/Orc/LookupAndRecordAddrsTest.cpp b/llvm/unittests/ExecutionEngine/Orc/LookupAndRecordAddrsTest.cpp
index 05ea919d4131c9..f62151de77a4bc 100644
--- a/llvm/unittests/ExecutionEngine/Orc/LookupAndRecordAddrsTest.cpp
+++ b/llvm/unittests/ExecutionEngine/Orc/LookupAndRecordAddrsTest.cpp
@@ -6,9 +6,9 @@
//
//===----------------------------------------------------------------------===//
-#include "OrcTestCommon.h"
-
#include "llvm/ExecutionEngine/Orc/LookupAndRecordAddrs.h"
+#include "OrcTestCommon.h"
+#include "llvm/ExecutionEngine/Orc/AbsoluteSymbols.h"
#include "llvm/Support/MSVCErrorWorkarounds.h"
#include "llvm/Testing/Support/Error.h"
diff --git a/llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp b/llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp
index 20db572417d5f6..083a924ce9aa16 100644
--- a/llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp
+++ b/llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp
@@ -1,6 +1,7 @@
#include "llvm/ExecutionEngine/Orc/ReOptimizeLayer.h"
#include "OrcTestCommon.h"
#include "llvm/ExecutionEngine/JITLink/JITLinkMemoryManager.h"
+#include "llvm/ExecutionEngine/Orc/AbsoluteSymbols.h"
#include "llvm/ExecutionEngine/Orc/CompileUtils.h"
#include "llvm/ExecutionEngine/Orc/ExecutorProcessControl.h"
#include "llvm/ExecutionEngine/Orc/IRCompileLayer.h"
>From 0e936e375e61ed2c85c5e9fc53c5a4ac01cf9ed1 Mon Sep 17 00:00:00 2001
From: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: Mon, 11 Nov 2024 00:40:10 +0000
Subject: [PATCH 28/31] [gn build] Port dc11c0601577
---
llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
index 25436c3cdb47d5..b18a8eb5995bb7 100644
--- a/llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
@@ -15,6 +15,7 @@ static_library("Orc") {
"//llvm/lib/WindowsDriver",
]
sources = [
+ "AbsoluteSymbols.cpp",
"COFFPlatform.cpp",
"COFFVCRuntimeSupport.cpp",
"CompileOnDemandLayer.cpp",
>From 3e30b365c1ec95f0cfb62c3cfdf4f6f1c824c0bd Mon Sep 17 00:00:00 2001
From: Doug Wyatt <doug at sonosphere.com>
Date: Sun, 10 Nov 2024 17:02:50 -0800
Subject: [PATCH 29/31] [Clang] SemaFunctionEffects: When verifying a function,
ignore any conditional noexcept expression. (#115342)
---------
Co-authored-by: Doug Wyatt <dwyatt at apple.com>
---
clang/lib/Sema/SemaFunctionEffects.cpp | 19 +++++++++++++++++--
.../Sema/attr-nonblocking-constraints.cpp | 14 ++++++++++++--
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Sema/SemaFunctionEffects.cpp b/clang/lib/Sema/SemaFunctionEffects.cpp
index ab728f24d8a271..a76a0a41276896 100644
--- a/clang/lib/Sema/SemaFunctionEffects.cpp
+++ b/clang/lib/Sema/SemaFunctionEffects.cpp
@@ -972,6 +972,7 @@ class Analyzer {
CallableInfo &CurrentCaller;
ViolationSite VSite;
const Expr *TrailingRequiresClause = nullptr;
+ const Expr *NoexceptExpr = nullptr;
FunctionBodyASTVisitor(Analyzer &Outer,
PendingFunctionAnalysis &CurrentFunction,
@@ -986,9 +987,22 @@ class Analyzer {
if (auto *Dtor = dyn_cast<CXXDestructorDecl>(CurrentCaller.CDecl))
followDestructor(dyn_cast<CXXRecordDecl>(Dtor->getParent()), Dtor);
- if (auto *FD = dyn_cast<FunctionDecl>(CurrentCaller.CDecl))
+ if (auto *FD = dyn_cast<FunctionDecl>(CurrentCaller.CDecl)) {
TrailingRequiresClause = FD->getTrailingRequiresClause();
+ // Note that FD->getType->getAs<FunctionProtoType>() can yield a
+ // noexcept Expr which has been boiled down to a constant expression.
+ // Going through the TypeSourceInfo obtains the actual expression which
+ // will be traversed as part of the function -- unless we capture it
+ // here and have TraverseStmt skip it.
+ if (TypeSourceInfo *TSI = FD->getTypeSourceInfo()) {
+ if (FunctionProtoTypeLoc TL =
+ TSI->getTypeLoc().getAs<FunctionProtoTypeLoc>())
+ if (const FunctionProtoType *FPT = TL.getTypePtr())
+ NoexceptExpr = FPT->getNoexceptExpr();
+ }
+ }
+
// Do an AST traversal of the function/block body
TraverseDecl(const_cast<Decl *>(CurrentCaller.CDecl));
}
@@ -1269,7 +1283,8 @@ class Analyzer {
// We skip the traversal of lambdas (beyond their captures, see
// TraverseLambdaExpr below), so just caching this from our constructor
// should suffice.
- if (Statement != TrailingRequiresClause)
+ // The exact same is true for a conditional `noexcept()` clause.
+ if (Statement != TrailingRequiresClause && Statement != NoexceptExpr)
return Base::TraverseStmt(Statement);
return true;
}
diff --git a/clang/test/Sema/attr-nonblocking-constraints.cpp b/clang/test/Sema/attr-nonblocking-constraints.cpp
index 19a4c3b7942b12..cc9108c0a4fbd6 100644
--- a/clang/test/Sema/attr-nonblocking-constraints.cpp
+++ b/clang/test/Sema/attr-nonblocking-constraints.cpp
@@ -388,7 +388,7 @@ void nb26() [[clang::nonblocking]] {
abort_wrapper(); // no diagnostic
}
-// --- Make sure we don't traverse a requires clause. ---
+// --- Make sure we don't traverse requires and noexcept clauses. ---
// Apparently some requires clauses are able to be collapsed into a constant before the nonblocking
// analysis sees any function calls. This example (extracted from a real-world case where
@@ -420,6 +420,7 @@ class expected {
constexpr expected()
{}
+ // This is a deliberate corruption of the real implementation for simplicity.
constexpr expected(const expected&)
requires(is_copy_constructible_v<_Tp> && is_copy_constructible_v<_Err>)
= default;
@@ -428,11 +429,20 @@ class expected {
void test() [[clang::nonblocking]]
{
expected<int, int> a;
- auto b = a;
+ auto b = a; // Copy constructor.
}
} // namespace ExpectedTest
+// Make sure a function call in a noexcept() clause is ignored.
+constexpr bool foo() [[clang::nonblocking(false)]] { return true; }
+void nb27() noexcept(foo()) [[clang::nonblocking]] {}
+
+// Make sure that simple type traits don't cause violations.
+void nb28() [[clang::nonblocking]] {
+ bool x = __is_constructible(int, const int&);
+}
+
// --- nonblocking implies noexcept ---
#pragma clang diagnostic warning "-Wperf-constraint-implies-noexcept"
>From e375c0f7d0c8f4c49ff2a430da0c3a7d058e9cf3 Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Mon, 11 Nov 2024 09:50:38 +0800
Subject: [PATCH 30/31] [RISCV][Clang] Add RequiredFeatures to zvfh intrinsics
(#115436)
This is a follow-up patch for
https://github.com/llvm/llvm-project/pull/101811.
That we can remove the type checking for fp16 from SemaRISCV.cpp.
Fixes: https://github.com/llvm/llvm-project/issues/101621 and
https://github.com/llvm/llvm-project/issues/94306
---
clang/include/clang/Basic/riscv_vector.td | 320 +++++++++++-------
.../clang/Basic/riscv_vector_common.td | 165 ++++++---
clang/lib/Sema/SemaRISCV.cpp | 14 -
3 files changed, 317 insertions(+), 182 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 74b9a7fc753a62..c4d2afe407516c 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -1651,9 +1651,13 @@ let ManualCodegen = [{
// 13.5. Vector Widening Floating-Point Multiply
let Log2LMUL = [-2, -1, 0, 1, 2] in {
- defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "xf",
- [["vv", "w", "wvvu"],
+ defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "f",
+ [["vv", "w", "wvvu"],
["vf", "w", "wveu"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "x",
+ [["vv", "w", "wvvu"],
+ ["vf", "w", "wveu"]]>;
}
}
// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
@@ -1663,9 +1667,13 @@ let ManualCodegen = [{
// 13.5. Vector Widening Floating-Point Multiply
let Log2LMUL = [-2, -1, 0, 1, 2] in {
- defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "xf",
- [["vv", "w", "wvv"],
+ defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "f",
+ [["vv", "w", "wvv"],
["vf", "w", "wve"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "x",
+ [["vv", "w", "wvv"],
+ ["vf", "w", "wve"]]>;
}
}
}
@@ -1846,20 +1854,30 @@ let ManualCodegen = [{
}] in {
let HasFRMRoundModeOp = 1 in {
// 13.8. Vector Floating-Point Square-Root Instruction
- defm vfsqrt : RVVOutBuiltinSet<"vfsqrt", "xfd", [["v", "v", "vvu"]]>;
+ defm vfsqrt : RVVOutBuiltinSet<"vfsqrt", "fd", [["v", "v", "vvu"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm vfsqrt : RVVOutBuiltinSet<"vfsqrt", "x", [["v", "v", "vvu"]]>;
// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
- defm vfrec7 : RVVOutBuiltinSet<"vfrec7", "xfd", [["v", "v", "vvu"]]>;
+ defm vfrec7 : RVVOutBuiltinSet<"vfrec7", "fd", [["v", "v", "vvu"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm vfrec7 : RVVOutBuiltinSet<"vfrec7", "x", [["v", "v", "vvu"]]>;
}
// 13.8. Vector Floating-Point Square-Root Instruction
- defm vfsqrt : RVVOutBuiltinSet<"vfsqrt", "xfd", [["v", "v", "vv"]]>;
+ defm vfsqrt : RVVOutBuiltinSet<"vfsqrt", "fd", [["v", "v", "vv"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm vfsqrt : RVVOutBuiltinSet<"vfsqrt", "x", [["v", "v", "vv"]]>;
// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
- defm vfrec7 : RVVOutBuiltinSet<"vfrec7", "xfd", [["v", "v", "vv"]]>;
+ defm vfrec7 : RVVOutBuiltinSet<"vfrec7", "fd", [["v", "v", "vv"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm vfrec7 : RVVOutBuiltinSet<"vfrec7", "x", [["v", "v", "vv"]]>;
}
// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
-defm vfrsqrt7 : RVVOutBuiltinSet<"vfrsqrt7", "xfd", [["v", "v", "vv"]]>;
+defm vfrsqrt7 : RVVOutBuiltinSet<"vfrsqrt7", "fd", [["v", "v", "vv"]]>;
+let RequiredFeatures = ["Zvfh"] in
+ defm vfrsqrt7 : RVVOutBuiltinSet<"vfrsqrt7", "x", [["v", "v", "vv"]]>;
// 13.11. Vector Floating-Point MIN/MAX Instructions
defm vfmin : RVVFloatingBinBuiltinSet;
@@ -1870,8 +1888,12 @@ defm vfsgnj : RVVFloatingBinBuiltinSet;
defm vfsgnjn : RVVFloatingBinBuiltinSet;
defm vfsgnjx : RVVFloatingBinBuiltinSet;
}
-defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "xfd">;
-defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "xfd">;
+defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "fd">;
+let RequiredFeatures = ["Zvfh"] in
+ defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "x">;
+defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "fd">;
+let RequiredFeatures = ["Zvfh"] in
+ defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "x">;
// 13.13. Vector Floating-Point Compare Instructions
let MaskedPolicyScheme = HasPassthruOperand,
@@ -1885,8 +1907,11 @@ defm vmfge : RVVFloatingMaskOutBuiltinSet;
}
// 13.14. Vector Floating-Point Classify Instruction
-let Name = "vfclass_v", UnMaskedPolicyScheme = HasPassthruOperand in
- def vfclass : RVVOp0Builtin<"Uv", "Uvv", "xfd">;
+let UnMaskedPolicyScheme = HasPassthruOperand in {
+defm vfclass : RVVOp0BuiltinSet<"vfclass", "fd", [["v", "Uv", "Uvv"]]>;
+let RequiredFeatures = ["Zvfh"] in
+ defm vfclass : RVVOp0BuiltinSet<"vfclass", "x", [["v", "Uv", "Uvv"]]>;
+}
// 13.15. Vector Floating-Point Merge Instruction
// C/C++ Operand: (mask, op1, op2, vl), Builtin: (op1, op2, mask, vl)
@@ -1907,8 +1932,11 @@ let HasMasked = false,
let RequiredFeatures = ["Zvfbfmin"] in
defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "y",
[["vvm", "v", "vvvm"]]>;
- defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "xfd",
+ defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "fd",
[["vfm", "v", "vvem"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "x",
+ [["vfm", "v", "vvem"]]>;
}
// 13.16. Vector Floating-Point Move Instruction
@@ -1916,55 +1944,71 @@ let HasMasked = false,
UnMaskedPolicyScheme = HasPassthruOperand,
SupportOverloading = false,
MaskedPolicyScheme = NonePolicy,
- OverloadedName = "vfmv_v" in
- defm vfmv_v : RVVOutBuiltinSet<"vfmv_v_f", "xfd",
- [["f", "v", "ve"]]>;
+ OverloadedName = "vfmv_v" in {
+ defm vfmv_v : RVVOutBuiltinSet<"vfmv_v_f", "fd",
+ [["f", "v", "ve"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm vfmv_v : RVVOutBuiltinSet<"vfmv_v_f", "x",
+ [["f", "v", "ve"]]>;
+}
// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
let UnMaskedPolicyScheme = HasPassthruOperand in {
-def vfcvt_rtz_xu_f_v : RVVConvToUnsignedBuiltin<"vfcvt_rtz_xu">;
-def vfcvt_rtz_x_f_v : RVVConvToSignedBuiltin<"vfcvt_rtz_x">;
+let OverloadedName = "vfcvt_rtz_xu" in {
+ defm : RVVConvBuiltinSet<"vfcvt_rtz_xu_f_v", "fd", [["Uv", "Uvv"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfcvt_rtz_xu_f_v", "x", [["Uv", "Uvv"]]>;
+}
+let OverloadedName = "vfcvt_rtz_x" in {
+ defm : RVVConvBuiltinSet<"vfcvt_rtz_x_f_v", "fd", [["Iv", "Ivv"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfcvt_rtz_x_f_v", "x", [["Iv", "Ivv"]]>;
+}
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
- def vfwcvt_rtz_xu_f_v : RVVConvToWidenUnsignedBuiltin<"vfwcvt_rtz_xu">;
- def vfwcvt_rtz_x_f_v : RVVConvToWidenSignedBuiltin<"vfwcvt_rtz_x">;
- def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "si", "vfwcvt_f">;
- def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "si", "vfwcvt_f">;
- let RequiredFeatures = ["Zvfh"] in {
- let Name = "vfwcvt_f_xu_v",
- IRName = "vfwcvt_f_xu_v",
- MaskedIRName = "vfwcvt_f_xu_v_mask" in
- def : RVVConvBuiltin<"Fw", "FwUv", "c", "vfwcvt_f">;
- let Name = "vfwcvt_f_x_v",
- IRName = "vfwcvt_f_x_v",
- MaskedIRName = "vfwcvt_f_x_v_mask" in
- def : RVVConvBuiltin<"Fw", "Fwv", "c", "vfwcvt_f">;
- }
- def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "f", "vfwcvt_f">;
- let RequiredFeatures = ["Zvfhmin"] in
- def vfwcvt_f_f_v_fp16 : RVVConvBuiltin<"w", "wv", "x", "vfwcvt_f"> {
- let Name = "vfwcvt_f_f_v";
- let IRName = "vfwcvt_f_f_v";
- let MaskedIRName = "vfwcvt_f_f_v_mask";
+ let OverloadedName = "vfwcvt_rtz_xu" in {
+ defm : RVVConvBuiltinSet<"vfwcvt_rtz_xu_f_v", "f", [["Uw", "Uwv"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfwcvt_rtz_xu_f_v", "x", [["Uw", "Uwv"]]>;
+ }
+ let OverloadedName = "vfwcvt_rtz_x" in {
+ defm : RVVConvBuiltinSet<"vfwcvt_rtz_x_f_v", "f", [["Iw", "Iwv"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfwcvt_rtz_x_f_v", "x", [["Iw", "Iwv"]]>;
+ }
+ let OverloadedName = "vfwcvt_f" in {
+ defm : RVVConvBuiltinSet<"vfwcvt_f_xu_v", "si", [["Fw", "FwUv"]]>;
+ defm : RVVConvBuiltinSet<"vfwcvt_f_x_v", "si", [["Fw", "Fwv"]]>;
+ let RequiredFeatures = ["Zvfh"] in {
+ defm : RVVConvBuiltinSet<"vfwcvt_f_xu_v", "c", [["Fw", "FwUv"]]>;
+ defm : RVVConvBuiltinSet<"vfwcvt_f_x_v", "c", [["Fw", "Fwv"]]>;
}
+ }
+ let OverloadedName = "vfwcvt_f" in {
+ defm : RVVConvBuiltinSet<"vfwcvt_f_f_v", "f", [["w", "wv"]]>;
+ let RequiredFeatures = ["Zvfhmin"] in
+ defm : RVVConvBuiltinSet<"vfwcvt_f_f_v", "x", [["w", "wv"]]>;
+ }
}
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
- def vfncvt_rtz_xu_f_w : RVVConvToNarrowingUnsignedBuiltin<"vfncvt_rtz_xu">;
- def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
- let RequiredFeatures = ["Zvfh"] in {
- let Name = "vfncvt_rtz_xu_f_w",
- IRName = "vfncvt_rtz_xu_f_w",
- MaskedIRName = "vfncvt_rtz_xu_f_w_mask" in
- def : RVVConvBuiltin<"Uv", "UvFw", "c", "vfncvt_rtz_xu">;
- let Name = "vfncvt_rtz_x_f_w",
- IRName = "vfncvt_rtz_x_f_w",
- MaskedIRName = "vfncvt_rtz_x_f_w_mask" in
- def : RVVConvBuiltin<"Iv", "IvFw", "c", "vfncvt_rtz_x">;
+ let OverloadedName = "vfncvt_rtz_xu" in {
+ defm : RVVConvBuiltinSet<"vfncvt_rtz_xu_f_w", "si", [["Uv", "UvFw"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfncvt_rtz_xu_f_w", "c", [["Uv", "UvFw"]]>;
+ }
+ let OverloadedName = "vfncvt_rtz_x" in {
+ defm : RVVConvBuiltinSet<"vfncvt_rtz_x_f_w", "si", [["Iv", "IvFw"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfncvt_rtz_x_f_w", "c", [["Iv", "IvFw"]]>;
+ }
+ let OverloadedName = "vfncvt_rod_f" in {
+ defm : RVVConvBuiltinSet<"vfncvt_rod_f_f_w", "f", [["v", "vw"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfncvt_rod_f_f_w", "x", [["v", "vw"]]>;
}
- def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
// Zvfbfmin - Vector convert BF16 to FP32
@@ -2016,54 +2060,62 @@ let ManualCodegen = [{
}] in {
let HasFRMRoundModeOp = 1 in {
// 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions
- let OverloadedName = "vfcvt_x" in
- defm :
- RVVConvBuiltinSet<"vfcvt_x_f_v", "xfd", [["Iv", "Ivvu"]]>;
- let OverloadedName = "vfcvt_xu" in
- defm :
- RVVConvBuiltinSet<"vfcvt_xu_f_v", "xfd", [["Uv", "Uvvu"]]>;
+ let OverloadedName = "vfcvt_x" in {
+ defm : RVVConvBuiltinSet<"vfcvt_x_f_v", "fd", [["Iv", "Ivvu"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfcvt_x_f_v", "x", [["Iv", "Ivvu"]]>;
+ }
+ let OverloadedName = "vfcvt_xu" in {
+ defm : RVVConvBuiltinSet<"vfcvt_xu_f_v", "fd", [["Uv", "Uvvu"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfcvt_xu_f_v", "x", [["Uv", "Uvvu"]]>;
+ }
let OverloadedName = "vfcvt_f" in {
- defm :
- RVVConvBuiltinSet<"vfcvt_f_x_v", "xfd", [["v", "vIvu"]]>;
- defm :
- RVVConvBuiltinSet<"vfcvt_f_xu_v", "xfd", [["v", "vUvu"]]>;
+ defm : RVVConvBuiltinSet<"vfcvt_f_x_v", "fd", [["v", "vIvu"]]>;
+ defm : RVVConvBuiltinSet<"vfcvt_f_xu_v", "fd", [["v", "vUvu"]]>;
+ let RequiredFeatures = ["Zvfh"] in {
+ defm : RVVConvBuiltinSet<"vfcvt_f_x_v", "x", [["v", "vIvu"]]>;
+ defm : RVVConvBuiltinSet<"vfcvt_f_xu_v", "x", [["v", "vUvu"]]>;
+ }
}
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
- let OverloadedName = "vfwcvt_x" in
- defm :
- RVVConvBuiltinSet<"vfwcvt_x_f_v", "xf", [["Iw", "Iwvu"]]>;
- let OverloadedName = "vfwcvt_xu" in
- defm :
- RVVConvBuiltinSet<"vfwcvt_xu_f_v", "xf", [["Uw", "Uwvu"]]>;
+ let OverloadedName = "vfwcvt_x" in {
+ defm : RVVConvBuiltinSet<"vfwcvt_x_f_v", "f", [["Iw", "Iwvu"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfwcvt_x_f_v", "x", [["Iw", "Iwvu"]]>;
+ }
+ let OverloadedName = "vfwcvt_xu" in {
+ defm : RVVConvBuiltinSet<"vfwcvt_xu_f_v", "f", [["Uw", "Uwvu"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfwcvt_xu_f_v", "x", [["Uw", "Uwvu"]]>;
+ }
}
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
- let OverloadedName = "vfncvt_x" in
- defm :
- RVVConvBuiltinSet<"vfncvt_x_f_w", "si", [["Iv", "IvFwu"]]>;
- let OverloadedName = "vfncvt_xu" in
- defm :
- RVVConvBuiltinSet<"vfncvt_xu_f_w", "si", [["Uv", "UvFwu"]]>;
- let RequiredFeatures = ["Zvfh"] in {
- let OverloadedName = "vfncvt_x" in
- defm :
- RVVConvBuiltinSet<"vfncvt_x_f_w", "c", [["Iv", "IvFwu"]]>;
- let OverloadedName = "vfncvt_xu" in
- defm :
- RVVConvBuiltinSet<"vfncvt_xu_f_w", "c", [["Uv", "UvFwu"]]>;
+ let OverloadedName = "vfncvt_x" in {
+ defm : RVVConvBuiltinSet<"vfncvt_x_f_w", "si", [["Iv", "IvFwu"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfncvt_x_f_w", "c", [["Iv", "IvFwu"]]>;
+ }
+ let OverloadedName = "vfncvt_xu" in {
+ defm : RVVConvBuiltinSet<"vfncvt_xu_f_w", "si", [["Uv", "UvFwu"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfncvt_xu_f_w", "c", [["Uv", "UvFwu"]]>;
}
let OverloadedName = "vfncvt_f" in {
- defm :
- RVVConvBuiltinSet<"vfncvt_f_x_w", "xf", [["v", "vIwu"]]>;
- defm :
- RVVConvBuiltinSet<"vfncvt_f_xu_w", "xf", [["v", "vUwu"]]>;
+ defm : RVVConvBuiltinSet<"vfncvt_f_x_w", "f", [["v", "vIwu"]]>;
+ defm : RVVConvBuiltinSet<"vfncvt_f_xu_w", "f", [["v", "vUwu"]]>;
+ let RequiredFeatures = ["Zvfh"] in {
+ defm : RVVConvBuiltinSet<"vfncvt_f_x_w", "x", [["v", "vIwu"]]>;
+ defm : RVVConvBuiltinSet<"vfncvt_f_xu_w", "x", [["v", "vUwu"]]>;
+ }
}
let OverloadedName = "vfncvt_f" in {
defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "f", [["v", "vwu"]]>;
let RequiredFeatures = ["Zvfhmin"] in
- defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "x", [["v", "vwu"]]>;
+ defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "x", [["v", "vwu"]]>;
}
}
@@ -2074,54 +2126,62 @@ let ManualCodegen = [{
}
// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
- let OverloadedName = "vfcvt_x" in
- defm :
- RVVConvBuiltinSet<"vfcvt_x_f_v", "xfd", [["Iv", "Ivv"]]>;
- let OverloadedName = "vfcvt_xu" in
- defm :
- RVVConvBuiltinSet<"vfcvt_xu_f_v", "xfd", [["Uv", "Uvv"]]>;
+ let OverloadedName = "vfcvt_x" in {
+ defm : RVVConvBuiltinSet<"vfcvt_x_f_v", "fd", [["Iv", "Ivv"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfcvt_x_f_v", "x", [["Iv", "Ivv"]]>;
+ }
+ let OverloadedName = "vfcvt_xu" in {
+ defm : RVVConvBuiltinSet<"vfcvt_xu_f_v", "fd", [["Uv", "Uvv"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfcvt_xu_f_v", "x", [["Uv", "Uvv"]]>;
+ }
let OverloadedName = "vfcvt_f" in {
- defm :
- RVVConvBuiltinSet<"vfcvt_f_x_v", "xfd", [["v", "vIv"]]>;
- defm :
- RVVConvBuiltinSet<"vfcvt_f_xu_v", "xfd", [["v", "vUv"]]>;
+ defm : RVVConvBuiltinSet<"vfcvt_f_x_v", "fd", [["v", "vIv"]]>;
+ defm : RVVConvBuiltinSet<"vfcvt_f_xu_v", "fd", [["v", "vUv"]]>;
+ let RequiredFeatures = ["Zvfh"] in {
+ defm : RVVConvBuiltinSet<"vfcvt_f_x_v", "x", [["v", "vIv"]]>;
+ defm : RVVConvBuiltinSet<"vfcvt_f_xu_v", "x", [["v", "vUv"]]>;
+ }
}
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
- let OverloadedName = "vfwcvt_x" in
- defm :
- RVVConvBuiltinSet<"vfwcvt_x_f_v", "xf", [["Iw", "Iwv"]]>;
- let OverloadedName = "vfwcvt_xu" in
- defm :
- RVVConvBuiltinSet<"vfwcvt_xu_f_v", "xf", [["Uw", "Uwv"]]>;
+ let OverloadedName = "vfwcvt_x" in {
+ defm : RVVConvBuiltinSet<"vfwcvt_x_f_v", "f", [["Iw", "Iwv"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfwcvt_x_f_v", "x", [["Iw", "Iwv"]]>;
+ }
+ let OverloadedName = "vfwcvt_xu" in {
+ defm : RVVConvBuiltinSet<"vfwcvt_xu_f_v", "f", [["Uw", "Uwv"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfwcvt_xu_f_v", "x", [["Uw", "Uwv"]]>;
+ }
}
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
- let OverloadedName = "vfncvt_x" in
- defm :
- RVVConvBuiltinSet<"vfncvt_x_f_w", "si", [["Iv", "IvFw"]]>;
- let OverloadedName = "vfncvt_xu" in
- defm :
- RVVConvBuiltinSet<"vfncvt_xu_f_w", "si", [["Uv", "UvFw"]]>;
- let RequiredFeatures = ["Zvfh"] in {
- let OverloadedName = "vfncvt_x" in
- defm :
- RVVConvBuiltinSet<"vfncvt_x_f_w", "c", [["Iv", "IvFw"]]>;
- let OverloadedName = "vfncvt_xu" in
- defm :
- RVVConvBuiltinSet<"vfncvt_xu_f_w", "c", [["Uv", "UvFw"]]>;
+ let OverloadedName = "vfncvt_x" in {
+ defm : RVVConvBuiltinSet<"vfncvt_x_f_w", "si", [["Iv", "IvFw"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfncvt_x_f_w", "c", [["Iv", "IvFw"]]>;
+ }
+ let OverloadedName = "vfncvt_xu" in {
+ defm : RVVConvBuiltinSet<"vfncvt_xu_f_w", "si", [["Uv", "UvFw"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm : RVVConvBuiltinSet<"vfncvt_xu_f_w", "c", [["Uv", "UvFw"]]>;
}
let OverloadedName = "vfncvt_f" in {
- defm :
- RVVConvBuiltinSet<"vfncvt_f_x_w", "xf", [["v", "vIw"]]>;
- defm :
- RVVConvBuiltinSet<"vfncvt_f_xu_w", "xf", [["v", "vUw"]]>;
+ defm : RVVConvBuiltinSet<"vfncvt_f_x_w", "f", [["v", "vIw"]]>;
+ defm : RVVConvBuiltinSet<"vfncvt_f_xu_w", "f", [["v", "vUw"]]>;
+ let RequiredFeatures = ["Zvfh"] in {
+ defm : RVVConvBuiltinSet<"vfncvt_f_x_w", "x", [["v", "vIw"]]>;
+ defm : RVVConvBuiltinSet<"vfncvt_f_xu_w", "x", [["v", "vUw"]]>;
+ }
}
let OverloadedName = "vfncvt_f" in {
defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "f", [["v", "vw"]]>;
let RequiredFeatures = ["Zvfhmin"] in
- defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "x", [["v", "vw"]]>;
+ defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "x", [["v", "vw"]]>;
}
}
@@ -2281,15 +2341,24 @@ let HasMasked = false, MaskedPolicyScheme = NonePolicy in {
// 16.2. Floating-Point Scalar Move Instructions
let HasMasked = false, MaskedPolicyScheme = NonePolicy in {
- let HasVL = false, OverloadedName = "vfmv_f" in
- defm vfmv_f : RVVOp0BuiltinSet<"vfmv_f_s", "xfd",
+ let HasVL = false, OverloadedName = "vfmv_f" in {
+ defm vfmv_f : RVVOp0BuiltinSet<"vfmv_f_s", "fd",
+ [["s", "ve", "ev"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm vfmv_f : RVVOp0BuiltinSet<"vfmv_f_s", "x",
[["s", "ve", "ev"]]>;
+ }
let OverloadedName = "vfmv_s",
UnMaskedPolicyScheme = HasPassthruOperand,
- SupportOverloading = false in
- defm vfmv_s : RVVOutBuiltinSet<"vfmv_s_f", "xfd",
+ SupportOverloading = false in {
+ defm vfmv_s : RVVOutBuiltinSet<"vfmv_s_f", "fd",
+ [["f", "v", "ve"],
+ ["x", "Uv", "UvUe"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm vfmv_s : RVVOutBuiltinSet<"vfmv_s_f", "x",
[["f", "v", "ve"],
["x", "Uv", "UvUe"]]>;
+ }
}
// 16.3. Vector Slide Instructions
@@ -2325,7 +2394,10 @@ let RequiredFeatures = ["Zvfbfmin"] in {
defm vrgather : RVVOutBuiltinSet<"vrgather_vx", "y",
[["vx", "v", "vvz"]]>;
}
-defm vrgatherei16 : RVVOutBuiltinSet<"vrgatherei16_vv", "csilxfd",
+defm vrgatherei16 : RVVOutBuiltinSet<"vrgatherei16_vv", "csilfd",
+ [["vv", "v", "vv(Log2EEW:4)Uv"]]>;
+let RequiredFeatures = ["Zvfh"] in
+defm vrgatherei16 : RVVOutBuiltinSet<"vrgatherei16_vv", "x",
[["vv", "v", "vv(Log2EEW:4)Uv"]]>;
// unsigned type
defm vrgather : RVVOutBuiltinSet<"vrgather_vv", "csil",
diff --git a/clang/include/clang/Basic/riscv_vector_common.td b/clang/include/clang/Basic/riscv_vector_common.td
index b38ca7341361c4..ee06d740bb1686 100644
--- a/clang/include/clang/Basic/riscv_vector_common.td
+++ b/clang/include/clang/Basic/riscv_vector_common.td
@@ -458,52 +458,91 @@ let HasMaskedOffOperand = false in {
["vx", "Uv", "UvUvUeUv"]]>;
}
multiclass RVVFloatingTerBuiltinSet {
- defm "" : RVVOutOp1BuiltinSet<NAME, "xfd",
+ defm "" : RVVOutOp1BuiltinSet<NAME, "fd",
[["vv", "v", "vvvv"],
["vf", "v", "vvev"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVOutOp1BuiltinSet<NAME, "x",
+ [["vv", "v", "vvvv"],
+ ["vf", "v", "vvev"]]>;
}
multiclass RVVFloatingTerBuiltinSetRoundingMode {
- defm "" : RVVOutOp1BuiltinSet<NAME, "xfd",
+ defm "" : RVVOutOp1BuiltinSet<NAME, "fd",
[["vv", "v", "vvvvu"],
["vf", "v", "vvevu"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVOutOp1BuiltinSet<NAME, "x",
+ [["vv", "v", "vvvvu"],
+ ["vf", "v", "vvevu"]]>;
}
}
let HasMaskedOffOperand = false, Log2LMUL = [-2, -1, 0, 1, 2] in {
multiclass RVVFloatingWidenTerBuiltinSet {
- defm "" : RVVOutOp1Op2BuiltinSet<NAME, "xf",
+ defm "" : RVVOutOp1Op2BuiltinSet<NAME, "f",
[["vv", "w", "wwvv"],
["vf", "w", "wwev"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVOutOp1Op2BuiltinSet<NAME, "x",
+ [["vv", "w", "wwvv"],
+ ["vf", "w", "wwev"]]>;
}
multiclass RVVFloatingWidenTerBuiltinSetRoundingMode {
- defm "" : RVVOutOp1Op2BuiltinSet<NAME, "xf",
+ defm "" : RVVOutOp1Op2BuiltinSet<NAME, "f",
[["vv", "w", "wwvvu"],
["vf", "w", "wwevu"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVOutOp1Op2BuiltinSet<NAME, "x",
+ [["vv", "w", "wwvvu"],
+ ["vf", "w", "wwevu"]]>;
}
}
-multiclass RVVFloatingBinBuiltinSet
- : RVVOutOp1BuiltinSet<NAME, "xfd",
- [["vv", "v", "vvv"],
- ["vf", "v", "vve"]]>;
+multiclass RVVFloatingBinBuiltinSet {
+ defm "" : RVVOutOp1BuiltinSet<NAME, "fd",
+ [["vv", "v", "vvv"],
+ ["vf", "v", "vve"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVOutOp1BuiltinSet<NAME, "x",
+ [["vv", "v", "vvv"],
+ ["vf", "v", "vve"]]>;
+}
-multiclass RVVFloatingBinBuiltinSetRoundingMode
- : RVVOutOp1BuiltinSet<NAME, "xfd",
- [["vv", "v", "vvvu"],
- ["vf", "v", "vveu"]]>;
+multiclass RVVFloatingBinBuiltinSetRoundingMode {
+ defm "" : RVVOutOp1BuiltinSet<NAME, "fd",
+ [["vv", "v", "vvvu"],
+ ["vf", "v", "vveu"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVOutOp1BuiltinSet<NAME, "x",
+ [["vv", "v", "vvvu"],
+ ["vf", "v", "vveu"]]>;
+}
-multiclass RVVFloatingBinVFBuiltinSet
- : RVVOutOp1BuiltinSet<NAME, "xfd",
- [["vf", "v", "vve"]]>;
+multiclass RVVFloatingBinVFBuiltinSet {
+ defm "" : RVVOutOp1BuiltinSet<NAME, "fd",
+ [["vf", "v", "vve"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVOutOp1BuiltinSet<NAME, "x",
+ [["vf", "v", "vve"]]>;
+}
-multiclass RVVFloatingBinVFBuiltinSetRoundingMode
- : RVVOutOp1BuiltinSet<NAME, "xfd",
- [["vf", "v", "vveu"]]>;
+multiclass RVVFloatingBinVFBuiltinSetRoundingMode {
+ defm "" : RVVOutOp1BuiltinSet<NAME, "fd",
+ [["vf", "v", "vveu"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVOutOp1BuiltinSet<NAME, "x",
+ [["vf", "v", "vveu"]]>;
+}
-multiclass RVVFloatingMaskOutBuiltinSet
- : RVVOp0Op1BuiltinSet<NAME, "xfd",
- [["vv", "vm", "mvv"],
- ["vf", "vm", "mve"]]>;
+multiclass RVVFloatingMaskOutBuiltinSet {
+ defm "" : RVVOp0Op1BuiltinSet<NAME, "fd",
+ [["vv", "vm", "mvv"],
+ ["vf", "vm", "mve"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVOp0Op1BuiltinSet<NAME, "x",
+ [["vv", "vm", "mvv"],
+ ["vf", "vm", "mve"]]>;
+}
multiclass RVVFloatingMaskOutVFBuiltinSet
: RVVOp0Op1BuiltinSet<NAME, "fd",
@@ -547,8 +586,11 @@ class RVVMaskOp0Builtin<string prototype> : RVVOp0Builtin<"m", prototype, "c"> {
let UnMaskedPolicyScheme = HasPolicyOperand,
HasMaskedOffOperand = false in {
multiclass RVVSlideUpBuiltinSet {
- defm "" : RVVOutBuiltinSet<NAME, "csilxfd",
+ defm "" : RVVOutBuiltinSet<NAME, "csilfd",
[["vx","v", "vvvz"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVOutBuiltinSet<NAME, "x",
+ [["vx","v", "vvvz"]]>;
defm "" : RVVOutBuiltinSet<NAME, "csil",
[["vx","Uv", "UvUvUvz"]]>;
}
@@ -569,8 +611,11 @@ let UnMaskedPolicyScheme = HasPassthruOperand,
IntrinsicTypes = {ResultType, Ops.back()->getType()};
}] in {
multiclass RVVSlideDownBuiltinSet {
- defm "" : RVVOutBuiltinSet<NAME, "csilxfd",
+ defm "" : RVVOutBuiltinSet<NAME, "csilfd",
[["vx","v", "vvz"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVOutBuiltinSet<NAME, "x",
+ [["vx","v", "vvz"]]>;
defm "" : RVVOutBuiltinSet<NAME, "csil",
[["vx","Uv", "UvUvz"]]>;
}
@@ -611,20 +656,32 @@ let HasMaskedOffOperand = true in {
[["vs", "UvUSv", "USvUvUSv"]]>;
}
multiclass RVVFloatingReductionBuiltin {
- defm "" : RVVOutOp0BuiltinSet<NAME, "xfd",
+ defm "" : RVVOutOp0BuiltinSet<NAME, "fd",
[["vs", "vSv", "SvvSv"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVOutOp0BuiltinSet<NAME, "x",
+ [["vs", "vSv", "SvvSv"]]>;
}
multiclass RVVFloatingReductionBuiltinRoundingMode {
- defm "" : RVVOutOp0BuiltinSet<NAME, "xfd",
+ defm "" : RVVOutOp0BuiltinSet<NAME, "fd",
[["vs", "vSv", "SvvSvu"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVOutOp0BuiltinSet<NAME, "x",
+ [["vs", "vSv", "SvvSvu"]]>;
}
multiclass RVVFloatingWidenReductionBuiltin {
- defm "" : RVVOutOp0BuiltinSet<NAME, "xf",
+ defm "" : RVVOutOp0BuiltinSet<NAME, "f",
[["vs", "vSw", "SwvSw"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVOutOp0BuiltinSet<NAME, "x",
+ [["vs", "vSw", "SwvSw"]]>;
}
multiclass RVVFloatingWidenReductionBuiltinRoundingMode {
- defm "" : RVVOutOp0BuiltinSet<NAME, "xf",
+ defm "" : RVVOutOp0BuiltinSet<NAME, "f",
[["vs", "vSw", "SwvSwu"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVOutOp0BuiltinSet<NAME, "x",
+ [["vs", "vSw", "SwvSwu"]]>;
}
}
@@ -684,22 +741,42 @@ multiclass RVVUnsignedWidenOp0BinBuiltinSet
[["wv", "Uw", "UwUwUv"],
["wx", "Uw", "UwUwUe"]]>;
-multiclass RVVFloatingWidenBinBuiltinSet
- : RVVWidenBuiltinSet<NAME, "xf",
- [["vv", "w", "wvv"],
- ["vf", "w", "wve"]]>;
+multiclass RVVFloatingWidenBinBuiltinSet {
+ defm "" : RVVWidenBuiltinSet<NAME, "f",
+ [["vv", "w", "wvv"],
+ ["vf", "w", "wve"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVWidenBuiltinSet<NAME, "x",
+ [["vv", "w", "wvv"],
+ ["vf", "w", "wve"]]>;
+}
-multiclass RVVFloatingWidenBinBuiltinSetRoundingMode
- : RVVWidenBuiltinSet<NAME, "xf",
- [["vv", "w", "wvvu"],
- ["vf", "w", "wveu"]]>;
+multiclass RVVFloatingWidenBinBuiltinSetRoundingMode {
+ defm "" : RVVWidenBuiltinSet<NAME, "f",
+ [["vv", "w", "wvvu"],
+ ["vf", "w", "wveu"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVWidenBuiltinSet<NAME, "x",
+ [["vv", "w", "wvvu"],
+ ["vf", "w", "wveu"]]>;
+}
-multiclass RVVFloatingWidenOp0BinBuiltinSet
- : RVVWidenWOp0BuiltinSet<NAME # "_w", "xf",
- [["wv", "w", "wwv"],
- ["wf", "w", "wwe"]]>;
+multiclass RVVFloatingWidenOp0BinBuiltinSet {
+ defm "" : RVVWidenWOp0BuiltinSet<NAME # "_w", "f",
+ [["wv", "w", "wwv"],
+ ["wf", "w", "wwe"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVWidenWOp0BuiltinSet<NAME # "_w", "x",
+ [["wv", "w", "wwv"],
+ ["wf", "w", "wwe"]]>;
+}
-multiclass RVVFloatingWidenOp0BinBuiltinSetRoundingMode
- : RVVWidenWOp0BuiltinSet<NAME # "_w", "xf",
- [["wv", "w", "wwvu"],
- ["wf", "w", "wweu"]]>;
+multiclass RVVFloatingWidenOp0BinBuiltinSetRoundingMode {
+ defm "" : RVVWidenWOp0BuiltinSet<NAME # "_w", "f",
+ [["wv", "w", "wwvu"],
+ ["wf", "w", "wweu"]]>;
+ let RequiredFeatures = ["Zvfh"] in
+ defm "" : RVVWidenWOp0BuiltinSet<NAME # "_w", "x",
+ [["wv", "w", "wwvu"],
+ ["wf", "w", "wweu"]]>;
+}
diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index e63d605349e060..163f7129a7b42b 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -282,20 +282,6 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI)
continue;
- // TODO: Remove the check below and use RequiredFeatures in
- // riscv_vector.td to check the intrinsics instead, the type check should
- // be done in checkRVVTypeSupport. This check also not able to work on the
- // intrinsics that have Float16 but the BaseType is not Float16 such as
- // `vfcvt_f_x_v`.
- if (BaseType == BasicType::Float16) {
- if ((Record.RequiredExtensions & RVV_REQ_Zvfhmin) == RVV_REQ_Zvfhmin) {
- if (!TI.hasFeature("zvfhmin"))
- continue;
- } else if (!TI.hasFeature("zvfh")) {
- continue;
- }
- }
-
// Expanded with different LMUL.
for (int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) {
if (!(Record.Log2LMULMask & (1 << (Log2LMUL + 3))))
>From 943bd9557507efdb84e31a67b78d63f78a7f7b8e Mon Sep 17 00:00:00 2001
From: Matthias Springer <mspringer at nvidia.com>
Date: Mon, 11 Nov 2024 03:32:55 +0100
Subject: [PATCH 31/31] [mlir][IR][NFC] `PostDominanceInfo`: Mark all functions
as `const`
Same as `DominanceInfo`, all functions should be `const`.
---
mlir/include/mlir/IR/Dominance.h | 8 ++++----
mlir/lib/IR/Dominance.cpp | 3 ++-
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/mlir/include/mlir/IR/Dominance.h b/mlir/include/mlir/IR/Dominance.h
index 95c99bd59f7b2f..66b9456533ae04 100644
--- a/mlir/include/mlir/IR/Dominance.h
+++ b/mlir/include/mlir/IR/Dominance.h
@@ -202,20 +202,20 @@ class PostDominanceInfo : public detail::DominanceInfoBase</*IsPostDom=*/true> {
using super::super;
/// Return true if operation A properly postdominates operation B.
- bool properlyPostDominates(Operation *a, Operation *b);
+ bool properlyPostDominates(Operation *a, Operation *b) const;
/// Return true if operation A postdominates operation B.
- bool postDominates(Operation *a, Operation *b) {
+ bool postDominates(Operation *a, Operation *b) const {
return a == b || properlyPostDominates(a, b);
}
/// Return true if the specified block A properly postdominates block B.
- bool properlyPostDominates(Block *a, Block *b) {
+ bool properlyPostDominates(Block *a, Block *b) const {
return super::properlyDominates(a, b);
}
/// Return true if the specified block A postdominates block B.
- bool postDominates(Block *a, Block *b) {
+ bool postDominates(Block *a, Block *b) const {
return a == b || properlyPostDominates(a, b);
}
};
diff --git a/mlir/lib/IR/Dominance.cpp b/mlir/lib/IR/Dominance.cpp
index 31f7e7dbc925ce..62477a823acaaf 100644
--- a/mlir/lib/IR/Dominance.cpp
+++ b/mlir/lib/IR/Dominance.cpp
@@ -327,7 +327,8 @@ bool DominanceInfo::properlyDominates(Value a, Operation *b) const {
//===----------------------------------------------------------------------===//
/// Returns true if statement 'a' properly postdominates statement b.
-bool PostDominanceInfo::properlyPostDominates(Operation *a, Operation *b) {
+bool PostDominanceInfo::properlyPostDominates(Operation *a,
+ Operation *b) const {
auto *aBlock = a->getBlock(), *bBlock = b->getBlock();
assert(aBlock && bBlock && "operations must be in a block");
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