[llvm-branch-commits] [llvm] [AMDGPU] Fix (PR #115505)
Shilei Tian via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Nov 8 08:09:13 PST 2024
https://github.com/shiltian created https://github.com/llvm/llvm-project/pull/115505
None
>From 8162e61b66ee56e476cf4987a9faff89dfdfc3d0 Mon Sep 17 00:00:00 2001
From: Shilei Tian <i at tianshilei.me>
Date: Tue, 29 Oct 2024 01:29:40 -0400
Subject: [PATCH] [AMDGPU] Fix
---
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index 13a2db7a87b437..8e3208abaec9a5 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -59,9 +59,18 @@ static MCRegister findScratchNonCalleeSaveRegister(
if (Unused)
return findUnusedRegister(MRI, LiveUnits, RC);
+ dbgs() << "--------\n";
+
for (MCRegister Reg : RC) {
- if (LiveUnits.available(Reg) && !MRI.isReserved(Reg))
+ dbgs() << "reg " << Reg << " avail? " << LiveUnits.available(Reg)
+ << ", reserved? " << MRI.isReserved(Reg) << "\n";
+ }
+
+ for (MCRegister Reg : RC) {
+ if (LiveUnits.available(Reg) && !MRI.isReserved(Reg)) {
+ dbgs() << "--------choose reg " << Reg << '\n';
return Reg;
+ }
}
return MCRegister();
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